https://gcc.gnu.org/g:d3d6b2a1fba366ea71379e6564758993cb5327c8
commit r17-3882-gd3d6b2a1fba366ea71379e6564758993cb5327c8 Author: Kito Cheng <[email protected]> Date: Thu Aug 20 22:34:01 2026 +0800 RISC-V: Add MVENDORID, MARCHID and MIMPID for 6 RISC-V cores Source: - sifive-p550 and sifive-p870-d from our downstream. - sifive-u74 and spacemit-x60 from gcc compiler farm. - spacemit-x100/spacemit-a100. from my own board gcc/ChangeLog: * config/riscv/riscv-cores.def (RISCV_CORE): Fill in MVENDORID, MARCHID and MIMPID for sifive-u74, sifive-p550, sifive-p870-d, spacemit-x60, spacemit-x100 and spacemit-a100. Diff: --- gcc/config/riscv/riscv-cores.def | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def index cd43444615f3..7e10a3839c1c 100644 --- a/gcc/config/riscv/riscv-cores.def +++ b/gcc/config/riscv/riscv-cores.def @@ -154,9 +154,9 @@ RISCV_CORE("sifive-u54", "rv64imafdc", "sifive-5-series", /* MARCHID */ UNKNOWN_ID, /* MIMPID */ UNKNOWN_ID) RISCV_CORE("sifive-u74", "rv64imafdc", "sifive-7-series", - /* MVENDORID */ UNKNOWN_ID, - /* MARCHID */ UNKNOWN_ID, - /* MIMPID */ UNKNOWN_ID) + /* MVENDORID */ 0x489, + /* MARCHID */ 0x8000000000000007ULL, + /* MIMPID */ 0x4210427ULL) RISCV_CORE("sifive-x280", "rv64imafdcv_zfh_zba_zbb_zvfh_zvl512b", "sifive-7-series", /* MVENDORID */ UNKNOWN_ID, @@ -171,9 +171,9 @@ RISCV_CORE("sifive-p450", "rv64imafdc_za64rs_zic64b_zicbom_zicbop_zicboz_" /* MIMPID */ UNKNOWN_ID) RISCV_CORE("sifive-p550", "rv64imafdc_zifencei_zfhmin_zba_zbb", "sifive-p550", - /* MVENDORID */ UNKNOWN_ID, - /* MARCHID */ UNKNOWN_ID, - /* MIMPID */ UNKNOWN_ID) + /* MVENDORID */ 0x489, + /* MARCHID */ 0x8000000000000008ULL, + /* MIMPID */ 0x6220425ULL) RISCV_CORE("sifive-p670", "rv64imafdcv_za64rs_zic64b_zicbom_zicbop_zicboz_" "ziccamoa_ziccif_zicclsm_ziccrse_zicsr_zifencei_" "zihintntl_zihintpause_zihpm_zfhmin_zba_zbb_zbs_" @@ -188,9 +188,9 @@ RISCV_CORE("sifive-p870-d", "rv64imafdcbv_zic64b_zicbom_zicbop_zicboz_" "za64rs_zama16b_zawrs_zfa_zfh_zcb_zcmop_zkr_zkt_" "zvbb_zvfbfwma_zvfh_zvfhmin_zvknc_zvksg", "sifive-p870-d", - /* MVENDORID */ UNKNOWN_ID, - /* MARCHID */ UNKNOWN_ID, - /* MIMPID */ UNKNOWN_ID) + /* MVENDORID */ 0x489, + /* MARCHID */ 0x8000000000000109ULL, + /* MIMPID */ 0x14250606ULL) RISCV_CORE("thead-c906", "rv64imafdc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_" "xtheadcondmov_xtheadfmemidx_xtheadmac_" @@ -391,26 +391,26 @@ RISCV_CORE("spacemit-x60", "rva22u64_v_zicond_zifencei_zihintntl_zihpm_zfh_zb "zbkc_zvfh_zvfhmin_zvkt_zvl256b_smepmp_sscofpmf_sstc_" "svinval_svnapot_svpbmt_xsmtvdot", "spacemit-x60", - /* MVENDORID */ UNKNOWN_ID, - /* MARCHID */ UNKNOWN_ID, - /* MIMPID */ UNKNOWN_ID) + /* MVENDORID */ 0x710, + /* MARCHID */ 0x8000000058000001ULL, + /* MIMPID */ 0x1000000049772200ULL) RISCV_CORE("spacemit-x100", "rva23s64_smepmp_smnpm_smstateen_sspm_zbc_zbkc_" "zfbfmin_zfh_zvbc_zvfbfwma_zvfh_zvknc_zvkng_zvknha_" "zvksc_zvksg_zvl256b_xsmtvdot", "spacemit-x100", - /* MVENDORID */ UNKNOWN_ID, - /* MARCHID */ UNKNOWN_ID, - /* MIMPID */ UNKNOWN_ID) + /* MVENDORID */ 0x710, + /* MARCHID */ 0x8000000058000002ULL, + /* MIMPID */ 0x33d8a600ULL) RISCV_CORE("spacemit-a100", "rva23u64_zfh_zbc_zbkc_zfbfmin_smepmp_smnpm_" "smstateen_sscofpmf_ssnpm_sspm_ssstateen_sstc_svinval_" "svnapot_svpbmt_zifencei_zvfh_zvfbfwma_zvkng_zvknha_" "zvknc_zvksc_zvksg_zvl1024b_xsmtvdotii", "spacemit-a100", - /* MVENDORID */ UNKNOWN_ID, - /* MARCHID */ UNKNOWN_ID, - /* MIMPID */ UNKNOWN_ID) + /* MVENDORID */ 0x710, + /* MARCHID */ 0x8000000041000002ULL, + /* MIMPID */ 0x10000000d5686200ULL) #undef RISCV_CORE #undef RISCV_CORE_ALIAS
