https://gcc.gnu.org/g:63fa52f94b89eefb8d56829d53bb8a59015f0bb6
commit r17-3914-g63fa52f94b89eefb8d56829d53bb8a59015f0bb6 Author: Pan Li <[email protected]> Date: Wed Sep 2 13:07:25 2026 +0800 RISC-V: Allow RVV register overlap for vwmaccu.vx undef Like vwmacc[u].vx, allow the rvv register overlap for the undef form of the dual widen ternary vx insn vwmaccu.vx. The undef form comes from the combine of the vec_duplicate and the vwmaccu.vv instead of the intrinsic. After that, all the dual widen ternary vx insns are able to overlap. gcc/ChangeLog: * config/riscv/vector.md: Leverage Wvr constraint. Signed-off-by: Pan Li <[email protected]> Diff: --- gcc/config/riscv/vector.md | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index bbdbe8eddd1d..e760f708faf2 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -9181,24 +9181,24 @@ }) (define_insn "*pred_widen_mul_plus_u_vx<mode>_undef" - [(set (match_operand:VWEXTI 0 "register_operand" "=&vr") + [(set (match_operand:VWEXTI 0 "register_operand" "=vr, vd") (if_then_else:VWEXTI (unspec:<VM> - [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1") - (match_operand 6 "vector_length_operand" " rvl") - (match_operand 7 "const_int_operand" " i") - (match_operand 8 "const_int_operand" " i") - (match_operand 9 "const_int_operand" " i") + [(match_operand:<VM> 1 "vector_mask_operand" "Wc1, vm") + (match_operand 6 "vector_length_operand" "rvl,rvl") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") + (match_operand 9 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus:VWEXTI (mult:VWEXTI (zero_extend:VWEXTI (vec_duplicate:<V_DOUBLE_TRUNC> - (match_operand:<VSUBEL> 3 "register_operand" " rJ"))) + (match_operand:<VSUBEL> 3 "register_operand" " rJ, rJ"))) (zero_extend:VWEXTI - (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))) - (match_operand:VWEXTI 5 "register_operand" " 0")) + (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "Wvr,Wvr"))) + (match_operand:VWEXTI 5 "register_operand" " 0, 0")) (match_operand:VWEXTI 2 "vector_undef_operand")))] "TARGET_VECTOR" "vwmaccu.vx\t%0,%z3,%4%p1"
