https://gcc.gnu.org/g:de2ea1f8b15f05264310a5e7c29328591c13de49
commit r17-5061-gde2ea1f8b15f05264310a5e7c29328591c13de49 Author: Jeff Law <[email protected]> Date: Sun Oct 11 09:19:22 2026 -0600 [RISC-V] Fix remaining AOP related regressions on the RISC-V port On RISC-V steering for AOP sometimes should steer towards PLUS, other times towards IOR. For example we want PLUS because we have shadd style insns that we can form and PLUS sometimes compresses better. Sometimes we want IOR because we can generate single bit manipulations. Things are made a bit more complicated by supporting rv32, rv64 and the various relevant extensions. Generally if all the arguments are registers, steer towards PLUS if ZBA is enabled. Otherwise steer towards IOR. The additional wrinkle here is that there aren't sub-word logicals on rv64, so we have to pun them to DImode and emit a 64bit operation. This fixes the pr80770-2 regression on both riscv32-elf and riscv64-elf and the pr58727 and pr93504 failures on riscv64-elf and is enough to make everything happy again. Bootstrapped and regression tested on the k3 and c920 (k1 in progress). gcc/ * config/riscv/riscv.md (aop<mode>3): New expander. Diff: --- gcc/config/riscv/riscv.md | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index cfac4c960bf1..e70439f5a0de 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -5503,6 +5503,35 @@ [(set_attr "type" "slt") (set_attr "mode" "<X:MODE>")]) +;; If the input operands are registers then we want to steer towards +;; ADD, otherwise steer towards IOR. +(define_expand "aop<mode>3" + [(set (match_operand:GPR 0 "register_operand") + (ior:GPR (match_operand:GPR 1 "register_operand") + (match_operand:GPR 2 "arith_operand")))] + "" + { + /* If we have shift-add insns and arguments are all registers, steer + towards PLUS, otherwise steer towards IOR. */ + if (TARGET_ZBA && REG_P (operands[2])) + emit_insn (gen_add<mode>3 (operands[0], operands[1], operands[2])); + else + { + /* We accept GPRs, so we need to do the right thing for SI on rv64. */ + if (GET_MODE (operands[0]) != word_mode) + { + operands[0] = gen_lowpart (word_mode, operands[0]); + operands[1] = gen_lowpart (word_mode, operands[1]); + operands[2] = gen_lowpart (word_mode, operands[2]); + emit_insn (gen_iordi3 (operands[0], operands[1], operands[2])); + } + else + emit_insn (gen_ior<mode>3 (operands[0], operands[1], operands[2])); + } + DONE; + } +) + (include "bitmanip.md") (include "crypto.md") (include "sync.md")
