https://gcc.gnu.org/g:fd7c5910162acddf1ae25bad82e4d4447d28ca8d
commit r17-5105-gfd7c5910162acddf1ae25bad82e4d4447d28ca8d Author: xiezhiheng <[email protected]> Date: Tue Oct 13 01:35:25 2026 +0000 aarch64: Treat all SVE as basic NEON instructions in DFA As mentioned in https://gcc.gnu.org/pipermail/gcc-patches/2026-October/733982.html, SVE instructions in the AArch64 backend do not have reservations set. So treat all SVE instructions as basic NEON instructions to avoid a large number of "nothing" entries in the DFA. For the args_1.c test case, I believe this is a separate issue that can be fixed in a separate patch. For now, I have restored the matching assembly to its previous form (see PR116604). For the other test cases, adjust the new instruction order. gcc/ChangeLog: * config/aarch64/aarch64.md (sve_type): Move to ... * config/aarch64/aarch64-sched-types.md: ... this new file. * config/arm/arm.md: Include aarch64-sched-types.md. * config/arm/cortex-a53.md: Treat SVE as NEON. * config/arm/cortex-a57.md: Likewise. gcc/testsuite/ChangeLog: * gcc.target/aarch64/popcnt11.c: Adjust instruction order. * gcc.target/aarch64/pr117557.c: Likewise. * gcc.target/aarch64/sve/noeffect2.c: Likewise. * gcc.target/aarch64/sve/pcs/args_1.c: Match the new assembly. * gcc.target/aarch64/sve/pred_clobber_4.c: Adjust instruction order. * gcc.target/aarch64/sve/widen_sum_1.c: Likewise. Signed-off-by: Zhiheng Xie <[email protected]> Diff: --- gcc/config/aarch64/aarch64-sched-types.md | 39 ++++++++++++++++++++++ gcc/config/aarch64/aarch64.md | 22 ++---------- gcc/config/arm/arm.md | 7 ++++ gcc/config/arm/cortex-a53.md | 6 +++- gcc/config/arm/cortex-a57.md | 4 +++ gcc/testsuite/gcc.target/aarch64/popcnt11.c | 12 +++---- gcc/testsuite/gcc.target/aarch64/pr117557.c | 7 ++-- gcc/testsuite/gcc.target/aarch64/sve/noeffect2.c | 2 +- gcc/testsuite/gcc.target/aarch64/sve/pcs/args_1.c | 19 +++++------ .../gcc.target/aarch64/sve/pred_clobber_4.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/widen_sum_1.c | 4 +++ 11 files changed, 81 insertions(+), 42 deletions(-) diff --git a/gcc/config/aarch64/aarch64-sched-types.md b/gcc/config/aarch64/aarch64-sched-types.md new file mode 100644 index 000000000000..d3668a9e2113 --- /dev/null +++ b/gcc/config/aarch64/aarch64-sched-types.md @@ -0,0 +1,39 @@ +;; Instruction Classification for AArch64. +;; +;; Copyright (C) 2026-2026 Free Software Foundation, Inc. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 3, or (at your +;; option) any later version. + +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; <http://www.gnu.org/licenses/>. + +;; Attribute that classifies SVE instructions by their functional type. +;; This attribute is currently only used for dispatch scheduling. +(define_attr "sve_type" + "none,\ + sve_pred_logical,sve_pred_cnt_ctrl,sve_pred_cnt_scalar,sve_pred_misc,\ + sve_pred_vec,\ + sve_fp_arith,sve_fp_mul,sve_fp_assoc_add,sve_fp_cmp,sve_fp_cvt,sve_fp_log,\ + sve_fp_exp,sve_fp_div,sve_fp_sqrt,sve_fp_reduc,sve_fp_misc,\ + sve_int_general,sve_int_shift,sve_int_mul,sve_int_dot,sve_int_cmp_set,\ + sve_int_extend,sve_int_extract,sve_int_cvt,sve_int_div,sve_int_index,\ + sve_int_match,sve_int_recip_est,sve_int_reduc,sve_int_accum,\ + sve_int_pmul,sve_int_bit_perm,\ + sve_load_pred,sve_load_1reg,sve_load_2reg,sve_load_3reg,sve_load_4reg,\ + sve_gatherload_32,sve_gatherload_64,\ + sve_store_pred,sve_store_1reg,sve_store_2reg,sve_store_3reg,sve_store_4reg,\ + sve_scatterstore_32,sve_scatterstore_64,\ + sve_ffr,\ + sve_crypto_sha3" + (const_string "none")) diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 988b00e55df8..51a04ff89f7d 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -491,6 +491,8 @@ ; to share pipeline descriptions. (include "../arm/types.md") +(include "aarch64-sched-types.md") + ;; It is important to set the fp or simd attributes to yes when a pattern ;; alternative uses the FP or SIMD register files, usually signified by use of ;; the 'w' constraint. This will ensure that the alternative will be @@ -684,26 +686,6 @@ ;; patterns. (define_attr "ldpstp" "ldp,stp,none" (const_string "none")) -;; Attribute that classifies SVE instructions by their functional type. -;; This attribute is currently only used for dispatch scheduling. -(define_attr "sve_type" - "none,\ - sve_pred_logical,sve_pred_cnt_ctrl,sve_pred_cnt_scalar,sve_pred_misc,\ - sve_pred_vec,\ - sve_fp_arith,sve_fp_mul,sve_fp_assoc_add,sve_fp_cmp,sve_fp_cvt,sve_fp_log,\ - sve_fp_exp,sve_fp_div,sve_fp_sqrt,sve_fp_reduc,sve_fp_misc,\ - sve_int_general,sve_int_shift,sve_int_mul,sve_int_dot,sve_int_cmp_set,\ - sve_int_extend,sve_int_extract,sve_int_cvt,sve_int_div,sve_int_index,\ - sve_int_match,sve_int_recip_est,sve_int_reduc,sve_int_accum,\ - sve_int_pmul,sve_int_bit_perm,\ - sve_load_pred,sve_load_1reg,sve_load_2reg,sve_load_3reg,sve_load_4reg,\ - sve_gatherload_32,sve_gatherload_64,\ - sve_store_pred,sve_store_1reg,sve_store_2reg,sve_store_3reg,sve_store_4reg,\ - sve_scatterstore_32,sve_scatterstore_64,\ - sve_ffr,\ - sve_crypto_sha3" - (const_string "none")) - ;; ------------------------------------------------------------------- ;; Pipeline descriptions and scheduling ;; ------------------------------------------------------------------- diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index febff17df0bf..785d341aa2aa 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -72,6 +72,13 @@ ;; Instruction classification types (include "types.md") +;; Included for cortex-a53 and cortex-a57 to use sve_type to handle +;; SVE instructions on AArch64. +;; TODO: Decouple the cortex-a57 description into an aarch64-only +;; "big core" description and use that as the base for big AArch64 +;; cores, unburdened by compatibility with arm. +(include "../aarch64/aarch64-sched-types.md") + ; IS_THUMB is set to 'yes' when we are generating Thumb code, and 'no' when ; generating ARM code. This is used to control the length of some insn ; patterns that share the same RTL in both ARM and Thumb code. diff --git a/gcc/config/arm/cortex-a53.md b/gcc/config/arm/cortex-a53.md index 87ad16564413..d5b59522ac12 100644 --- a/gcc/config/arm/cortex-a53.md +++ b/gcc/config/arm/cortex-a53.md @@ -446,7 +446,11 @@ neon_store4_4reg, neon_store4_4reg_q,\ neon_store4_one_lane, neon_store4_one_lane_q,\ neon_stp, neon_stp_q") - (const_string "advsimd_store_lots")] + (const_string "advsimd_store_lots") +;; Treat all SVE instructions as basic NEON instructions to avoid +;; lots of "nothing" in the DFA. + (not (eq_attr "sve_type" "none")) + (const_string "advsimd_alu")] (const_string "unknown"))) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; diff --git a/gcc/config/arm/cortex-a57.md b/gcc/config/arm/cortex-a57.md index 07003422e011..7a06d121c55d 100644 --- a/gcc/config/arm/cortex-a57.md +++ b/gcc/config/arm/cortex-a57.md @@ -241,6 +241,10 @@ ;; still a NEON type, treat it as a basic NEON type. This is better than ;; dropping it on the floor and making no assumptions about it whatsoever. (eq_attr "is_neon_type" "yes") + (const_string "neon_arith_basic") +;; Treat all SVE instructions as basic NEON instructions to avoid +;; lots of "nothing" in the DFA. + (not (eq_attr "sve_type" "none")) (const_string "neon_arith_basic")] (const_string "unknown"))) diff --git a/gcc/testsuite/gcc.target/aarch64/popcnt11.c b/gcc/testsuite/gcc.target/aarch64/popcnt11.c index e7e67de3572f..8a0e5532a27c 100644 --- a/gcc/testsuite/gcc.target/aarch64/popcnt11.c +++ b/gcc/testsuite/gcc.target/aarch64/popcnt11.c @@ -17,10 +17,10 @@ f_qi (unsigned char *a) /* ** f_hi: -** ldr h([0-9]+), \[x0\] ** ptrue (p[0-7]).b, vl8 -** cnt z\1.h, \2/m, z\1.h -** smov w0, v\1.h\[0\] +** ldr h([0-9]+), \[x0\] +** cnt z\2.h, \1/m, z\2.h +** smov w0, v\2.h\[0\] ** ret */ unsigned @@ -31,10 +31,10 @@ f_hi (unsigned short *a) /* ** f_si: -** ldr s([0-9]+), \[x0\] ** ptrue (p[0-7]).b, vl8 -** cnt z\1.s, \2/m, z\1.s -** umov x0, v\1.d\[0\] +** ldr s([0-9]+), \[x0\] +** cnt z\2.s, \1/m, z\2.s +** umov x0, v\2.d\[0\] ** ret */ unsigned diff --git a/gcc/testsuite/gcc.target/aarch64/pr117557.c b/gcc/testsuite/gcc.target/aarch64/pr117557.c index 80b3fde41109..858738e2cf55 100644 --- a/gcc/testsuite/gcc.target/aarch64/pr117557.c +++ b/gcc/testsuite/gcc.target/aarch64/pr117557.c @@ -11,11 +11,12 @@ /* **f: ** ... +** addvl x([0-9]+), x([0-9]+), #2 +** ... ** ld1w z[0-9]+.s, p([0-9]+)/z, \[x[0-9]+, z[0-9]+.s, sxtw\] ** ld1w z[0-9]+.s, p([0-9]+)/z, \[x[0-9]+, z[0-9]+.s, sxtw\] -** st1w z[0-9]+.s, p\1, \[x[0-9]+, z[0-9]+.s, sxtw\] -** incb x([0-9]+), all, mul #2 -** st1w z[0-9]+.s, p\2, \[x\3, z[0-9]+.s, sxtw\] +** st1w z[0-9]+.s, p\3, \[x\2, z[0-9]+.s, sxtw\] +** st1w z[0-9]+.s, p\4, \[x\1, z[0-9]+.s, sxtw\] ** ret ** ... */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/noeffect2.c b/gcc/testsuite/gcc.target/aarch64/sve/noeffect2.c index 04b7eb993e36..c619647fee0c 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/noeffect2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/noeffect2.c @@ -13,10 +13,10 @@ int b[N] = {0}; ** ... ** ld1w z[0-9]+\.s, p[0-9]+/z, \[x[0-9]+, x[0-9]+, lsl 2\] ** ld1w z[0-9]+\.s, p[0-9]+/z, \[x[0-9]+, x[0-9]+, lsl 2\] +** incw x[0-9]+ ** cmpgt p[0-9]+\.s, p[0-9]+/z, z[0-9]+\.s, z[0-9]+\.s ** b\.any \.L[0-9]+ ** ... -** incw x[0-9]+ ** whilelo p[0-9]+\.s, w[0-9]+, w[0-9]+ ** b\.any \.L[0-9]+ ** mov w0, 0 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_1.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_1.c index b020a0435239..ae481650d496 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_1.c @@ -6,18 +6,15 @@ /* ** callee_pred: -** brkpa (p[0-3])\.b, p0/z, p1\.b, p2\.b -** ( -** ldr (p[0-3]), \[x0\] -** ldr (p[0-3]), \[x1\] -** brkpb (p[0-3])\.b, \1/z, \2\.b, \3\.b +** addvl sp, sp, #-1 +** str p[0-9]+, \[sp\] +** ldr (p[0-9]+), \[x0\] +** brkpa (p[0-7])\.b, p0/z, p1\.b, p2\.b +** ldr (p[0-9]+), \[x1\] +** brkpb (p[0-7])\.b, \2/z, \1\.b, \3\.b ** brka p0\.b, \4/z, p3\.b -** | -** ldr (p[0-3]), \[x1\] -** ldr (p[0-3]), \[x0\] -** brkpb (p[0-3])\.b, \1/z, \6\.b, \5\.b -** brka p0\.b, \7/z, p3\.b -** ) +** ldr p[0-9]+, \[sp\] +** addvl sp, sp, #1 ** ret */ __SVBool_t __attribute__((noipa, optimize("schedule-insns"))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_4.c b/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_4.c index c0120afe5d52..73af2a8a3aec 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_4.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_4.c @@ -12,6 +12,7 @@ extern void use(svbool_t); ** foo: ** ... ** ptrue p0.b, all +** mov z[0-9]+.h, w0 ** cmplo p0.h, p0/z, z0.h, z[0-9]+.h ** ... */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/widen_sum_1.c b/gcc/testsuite/gcc.target/aarch64/sve/widen_sum_1.c index 3ae9d14dafd3..7aa6ee9f5af7 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/widen_sum_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/widen_sum_1.c @@ -19,6 +19,7 @@ ** cnth x[0-9]+ ** ... ** ptrue (p[0-7])\.b, all +** ... ** mov (z[0-9]+\.h), #1 ** ... ** ld1b (z[0-9]+\.h), \1/z, \[[^]]*\] @@ -36,6 +37,7 @@ DEF (sum_u8_long, unsigned char, long) ** cnth x[0-9]+ ** ... ** ptrue (p[0-7])\.b, all +** ... ** mov (z[0-9]+\.h), #1 ** ... ** ld1sb (z[0-9]+\.h), \1/z, \[[^]]*\] @@ -53,6 +55,7 @@ DEF (sum_s8_long, signed char, long) ** cntb x[0-9]+ ** ... ** ptrue (p[0-7])\.b, all +** ... ** mov (z[0-9]+\.b), #1 ** ... ** ld1b (z[0-9]+\.b), \1/z, \[[^]]*\] @@ -70,6 +73,7 @@ DEF (sum_u8_int, unsigned char, int) ** cntb x[0-9]+ ** ... ** ptrue (p[0-7])\.b, all +** ... ** mov (z[0-9]+\.b), #1 ** ... ** ld1b (z[0-9]+\.b), \1/z, \[[^]]*\]
