https://gcc.gnu.org/g:c7d983e54c1dbcf7906a0f359920cb5b54aa9bba
commit r17-5305-gc7d983e54c1dbcf7906a0f359920cb5b54aa9bba Author: Jeff Law <[email protected]> Date: Sun Oct 18 11:45:09 2026 -0600 [RISC-V] Fix mode goofs in RISC-V's bitmanip.md So two more issues in bitmanip.md found by LLM review. We should never have mismatched modes between the mode of an operator such as AND and the modes of its operands. Two patterns still have that bug in bitmanip.md. In this case the patters are conditional on TARGET_64BIT, so X is always DI. Additionally, the SI operation really should just have been DI. My first thought was to remove the patterns as they shouldn't have been matching, but that regresses in the testsuite. My guess is in the IL we've got a subreg sitting in there and the pattern matched the narrowing subreg as the SI argument. We can just take the full DI value instead and the right things just happen (we're masking off all but a few of the low bits as these are shift/rotate counts). Tested on riscv32-elf and riscv64-elf and bootstrap + regression tested on k3 and c920. Pushing to the trunk. LLM is still finding things of interest in here... gcc/ * config/riscv/bitmanip.md (*<bitmanip_optab>3_mask_si): Fix mode for masked shift count. (*<bitmanip_optab>si3_sext_mask): Likewise. Diff: --- gcc/config/riscv/bitmanip.md | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index af728c54835b..ab0bfb27c3c5 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -496,8 +496,8 @@ (bitmanip_rotate:SI (match_operand:SI 1 "register_operand" "r") (match_operator 3 "subreg_lowpart_operator" - [(and:X (match_operand:SI 2 "register_operand" "r") - (const_int 31))])))] + [(and:DI (match_operand:DI 2 "register_operand" "r") + (const_int 31))])))] "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)" "<bitmanip_insn>w\t%0,%1,%2" [(set_attr "type" "bitmanip") @@ -509,8 +509,8 @@ (bitmanip_rotate:SI (match_operand:SI 1 "register_operand" "r") (match_operator 3 "subreg_lowpart_operator" - [(and:X (match_operand:GPR 2 "register_operand" "r") - (const_int 31))]))))] + [(and:DI (match_operand:DI 2 "register_operand" "r") + (const_int 31))]))))] "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)" "<bitmanip_insn>w\t%0,%1,%2" [(set_attr "type" "bitmanip")
