PR64011 is actually a general problem on all target support bit insertion
instructions.
we overflow check at the start of store_bit_field_1, but that only check the
situation where the field lies completely outside the register, while there do
have situation where the field lies partly in the register, we need to adjust
bitsize for this partial overflow situation. Without this fix, pr48335-2.c on
big-endian will broken on those arch support bit insert instruction, like arm,
aarch64.
the testcase is just pr48335-2.c, before this patch is will ICE on arm and =
generate
invalid assembly on AArch64. after this patch, problem gone away.
ok for trunk?
bootstrap OK on x86-64 && aarch64.
no regression on x86-64
thanks.
gcc/
PR64011
* expmed.c (store_bit_field_using_insv): Adjust bitsize when there is
partial overflow.
diff --git a/gcc/expmed.c b/gcc/expmed.c
index 0304e46..61aec39 100644
--- a/gcc/expmed.c
+++ b/gcc/expmed.c
@@ -535,6 +535,16 @@ store_bit_field_using_insv (const extraction_insn *insv, rtx op0,
copy_back = true;
}
+ /* There are similar overflow check at the start of store_bit_field_1,
+ but that only check the situation where the field lies completely
+ outside the register, while there do have situation where the field
+ lies partialy in the register, we need to adjust bitsize for this
+ partial overflow situation. Without this fix, pr48335-2.c on big-endian
+ will broken on those arch support bit insert instruction, like arm, aarch64
+ etc. */
+ if (bitsize + bitnum > unit && bitnum < unit)
+ bitsize = unit - bitnum;
+
/* If BITS_BIG_ENDIAN is zero on a BYTES_BIG_ENDIAN machine, we count
"backwards" from the size of the unit we are inserting into.
Otherwise, we count bits from the most significant on a
