* gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vpadd.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vpmax.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vpmin.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc
new file mode 100644
index 0000000..7ac2ed4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc
@@ -0,0 +1,67 @@
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+ /* Basic test: y=OP(x), then store the result. */
+#define TEST_VPADD1(INSN, T1, T2, W, N)
\
+ VECT_VAR(vector_res, T1, W, N) = \
+ INSN##_##T2##W(VECT_VAR(vector, T1, W, N), \
+ VECT_VAR(vector, T1, W, N)); \
+ vst1##_##T2##W(VECT_VAR(result, T1, W, N), \
+ VECT_VAR(vector_res, T1, W, N))
+
+#define TEST_VPADD(INSN, T1, T2, W, N) \
+ TEST_VPADD1(INSN, T1, T2, W, N) \
+
+ /* No need for 64 bits variants. */
+ DECL_VARIABLE(vector, int, 8, 8);
+ DECL_VARIABLE(vector, int, 16, 4);
+ DECL_VARIABLE(vector, int, 32, 2);
+ DECL_VARIABLE(vector, uint, 8, 8);
+ DECL_VARIABLE(vector, uint, 16, 4);
+ DECL_VARIABLE(vector, uint, 32, 2);
+ DECL_VARIABLE(vector, float, 32, 2);
+
+ DECL_VARIABLE(vector_res, int, 8, 8);
+ DECL_VARIABLE(vector_res, int, 16, 4);
+ DECL_VARIABLE(vector_res, int, 32, 2);
+ DECL_VARIABLE(vector_res, uint, 8, 8);
+ DECL_VARIABLE(vector_res, uint, 16, 4);
+ DECL_VARIABLE(vector_res, uint, 32, 2);
+ DECL_VARIABLE(vector_res, float, 32, 2);
+
+ clean_results ();
+
+ /* Initialize input "vector" from "buffer". */
+ VLOAD(vector, buffer, , int, s, 8, 8);
+ VLOAD(vector, buffer, , int, s, 16, 4);
+ VLOAD(vector, buffer, , int, s, 32, 2);
+ VLOAD(vector, buffer, , uint, u, 8, 8);
+ VLOAD(vector, buffer, , uint, u, 16, 4);
+ VLOAD(vector, buffer, , uint, u, 32, 2);
+ VLOAD(vector, buffer, , float, f, 32, 2);
+
+ /* Apply a unary operator named INSN_NAME. */
+ TEST_VPADD(INSN_NAME, int, s, 8, 8);
+ TEST_VPADD(INSN_NAME, int, s, 16, 4);
+ TEST_VPADD(INSN_NAME, int, s, 32, 2);
+ TEST_VPADD(INSN_NAME, uint, u, 8, 8);
+ TEST_VPADD(INSN_NAME, uint, u, 16, 4);
+ TEST_VPADD(INSN_NAME, uint, u, 32, 2);
+ TEST_VPADD(INSN_NAME, float, f, 32, 2);
+
+ CHECK(TEST_MSG, int, 8, 8, PRIx32, expected, "");
+ CHECK(TEST_MSG, int, 16, 4, PRIx64, expected, "");
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 8, 8, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 16, 4, PRIx64, expected, "");
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
+ CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, "");
+}
+
+int main (void)
+{
+ FNNAME (INSN_NAME) ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadd.c
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadd.c
new file mode 100644
index 0000000..5ddfd3d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadd.c
@@ -0,0 +1,19 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vpadd
+#define TEST_MSG "VPADD"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xe1, 0xe5, 0xe9, 0xed,
+ 0xe1, 0xe5, 0xe9, 0xed };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xffe1, 0xffe5, 0xffe1, 0xffe5 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xffffffe1, 0xffffffe1 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0xe1, 0xe5, 0xe9, 0xed,
+ 0xe1, 0xe5, 0xe9, 0xed };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xffe1, 0xffe5, 0xffe1, 0xffe5 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffffe1, 0xffffffe1 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1f80000, 0xc1f80000 };
+
+#include "vpXXX.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmax.c
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmax.c
new file mode 100644
index 0000000..f27a9a9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmax.c
@@ -0,0 +1,20 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+
+#define INSN_NAME vpmax
+#define TEST_MSG "VPMAX"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xf1, 0xf3, 0xf5, 0xf7,
+ 0xf1, 0xf3, 0xf5, 0xf7 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff1, 0xfff3, 0xfff1, 0xfff3 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff1, 0xfffffff1 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf1, 0xf3, 0xf5, 0xf7,
+ 0xf1, 0xf3, 0xf5, 0xf7 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff1, 0xfff3, 0xfff1, 0xfff3 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff1, 0xfffffff1 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1700000, 0xc1700000 };
+
+#include "vpXXX.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmin.c
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmin.c
new file mode 100644
index 0000000..a7cb696
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmin.c
@@ -0,0 +1,20 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+
+#define INSN_NAME vpmin
+#define TEST_MSG "VPMIN"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xf0, 0xf2, 0xf4, 0xf6,
+ 0xf0, 0xf2, 0xf4, 0xf6 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff0, 0xfff2, 0xfff0, 0xfff2 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff0, 0xfffffff0 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf0, 0xf2, 0xf4, 0xf6,
+ 0xf0, 0xf2, 0xf4, 0xf6 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff0, 0xfff2, 0xfff0, 0xfff2 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0xfffffff0 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1800000, 0xc1800000 };
+
+#include "vpXXX.inc"
--
2.1.0
