Hi all we have merged the gcc-4_9-branch into linaro/gcc-4_9-branch up to revision 219502 as r219549. We have also backported this set of revisions:
* r209620 as r219434 : [AArch64] Support SISD variants of SCVTF,UCVTF * r209800 as r219597 : Add clobber_reg * r211075 as r219465 : Add execution tests of ARM REV intrinsics. * r211132 as r219435 : [AArch64] Fix ICE in aarch64_float_const_representable_p * r211783 as r219596 : [AArch32] Post-indexed addressing for NEON memory access * r211789 as r219517 : [AArch32] Improve 64 bit division performance (serie) * r211790 as r219517 : [AArch32] Improve 64 bit division performance (serie) * r211791 as r219517 : [AArch32] Improve 64 bit division performance (serie) * r211792 as r219517 : [AArch32] Improve 64 bit division performance (serie) * r211793 as r219517 : [AArch32] Improve 64 bit division performance (serie) * r211794 as r219517 : [AArch32] Improve 64 bit division performance (serie) * r211795 as r219517 : [AArch32] Improve 64 bit division performance (serie) * r211796 as r219517 : [AArch32] Improve 64 bit division performance (serie) * r211797 as r219517 : [AArch32] Improve 64 bit division performance (serie) * r215503 as r219436 : [AArch64] Switch to sched-pressure by default. * r216267 as r219518 : Add ACLE 2.0 predefined macros * r216547 as r219518 : Add ACLE 2.0 predefined macro __ARM_FEATURE_IDIV * r216548 as r219518 : fixes 216547 * r217072 as r219518 : Fix typo in definition of __ARM_FEATURE_IDIV * r217073 as r219518 : Fix typo in definition of __ARM_FEATURE_IDIV * r217192 as r219518 : Add ACLE arch-related predefined macros * r217362 as r219433 : Fix up BSL expander for floating point types * r217394 as r219522 : PR target/61997 - cc1plus ICE with aarch64 target using PCH and builtin functions * r217405 as r219518 : Add reference to ACLE and consolidate documentation * r217406 as r219518 : Remove unnecessary files * r217546 as r219433 : PR target/63724 * r217593 as r219516 : Add scheduler for ThunderX * r217661 as r219463 : Remove crypto extension from default for cortex-a53, cortex-a57 * r217691 as r219437 : [LRA] Relax one gcc_assert in lra-eliminate for fixed register * r217717 as r219464 : doloop pattern for -fmodulo-sched * r217768 as r219518 : more conditional macros defined in ACLE 2.0 * r218319 as r219438 : Revert 215321 * r218451 as r219584 : extend jump thread for finite state automata This will be part of our 2015.01 4.9 release. Thanks Yvan
