Hi all,
This patch fixes the PR by folding the ((x ^ y) & m) ^ x form of the RTL
to a bit-select instruction rather than the previous (x & ~m) | (y & m)
form.
This is in sync with the match.pd change that introduced the folding:
Author: mpolacek <mpolacek@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Wed Dec 17 11:48:33 2014 +0000
PR middle-end/63568
match.pd: Add (x & ~m) | (y & m) -> ((x ^ y) & m) ^ x pattern.
I decided to replace the previous pattern rather than add a new combine
pattern.
I initially thought of leaving the previous pattern in case we used some
target intrinsics to expand to the and-not-ior form in RTL, but I see
that all the relevant intrinsics in arm_neon.h are implemented using the
tree-level operators and so their combinations fold into this
xor-and-xor form.
This patch gets the gcc.target/aarch64/vbslq_u64_1.c test passing again,
so I'm not adding a new test.
Bootstrapped and tested on aarch64-linux.
Ok for trunk?
Thanks,
Kyrill
2014-01-16 Kyrylo Tkachov <kyrylo.tkac...@arm.com>
PR target/64448
* config/aarch64/aarch64-simd.md (aarch64_simd_bsl<mode>_internal):
Match xor-and-xor RTL pattern.commit 9db06d318d3d0626d9161204e8db18faf39271bb
Author: Kyrylo Tkachov <kyrylo.tkac...@arm.com>
Date: Fri Jan 9 09:59:15 2015 +0000
[AArch64] Match bfi with new folding ops
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 9651b99..495c6e7 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -1986,15 +1986,14 @@ (define_insn "aarch64_reduc_<maxmin_uns>_internal<mode>"
;; bif op0, op1, mask
(define_insn "aarch64_simd_bsl<mode>_internal"
- [(set (match_operand:VSDQ_I_DI 0 "register_operand" "=w,w,w")
- (ior:VSDQ_I_DI
+ [(set (match_operand:VSDQ_I_DI 0 "register_operand" "=w,w,w")
+ (xor:VSDQ_I_DI
(and:VSDQ_I_DI
- (not:<V_cmp_result>
- (match_operand:<V_cmp_result> 1 "register_operand" " 0,w,w"))
- (match_operand:VSDQ_I_DI 3 "register_operand" " w,0,w"))
- (and:VSDQ_I_DI
- (match_dup:<V_cmp_result> 1)
- (match_operand:VSDQ_I_DI 2 "register_operand" " w,w,0"))
+ (xor:VSDQ_I_DI
+ (match_operand:<V_cmp_result> 3 "register_operand" "w,0,w")
+ (match_operand:VSDQ_I_DI 2 "register_operand" "w,w,0"))
+ (match_operand:VSDQ_I_DI 1 "register_operand" "0,w,w"))
+ (match_dup:<V_cmp_result> 3)
))]
"TARGET_SIMD"
"@
