On 19 January 2015 at 14:39, Marcus Shawcroft <marcus.shawcr...@gmail.com> wrote: > On 13 January 2015 at 15:18, Christophe Lyon <christophe.l...@linaro.org> > wrote: >> >> * gcc.target/aarch64/advsimd-intrinsics/vmlX_lane.inc: New file. >> * gcc.target/aarch64/advsimd-intrinsics/vmla_lane.c: New file. >> * gcc.target/aarch64/advsimd-intrinsics/vmls_lane.c: New file. > > OK with Tejas' comment addressed. /Marcus
Here is what I have committed (removed poly, int8 and int64 variants). Christophe.
Index: gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlX_lane.inc =================================================================== --- gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlX_lane.inc (revision 0) +++ gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlX_lane.inc (working copy) @@ -0,0 +1,100 @@ +#define FNNAME1(NAME) exec_ ## NAME +#define FNNAME(NAME) FNNAME1(NAME) + +void FNNAME (INSN_NAME) (void) +{ +#define DECL_VMLX_LANE(VAR) \ + DECL_VARIABLE(VAR, int, 16, 4); \ + DECL_VARIABLE(VAR, int, 32, 2); \ + DECL_VARIABLE(VAR, uint, 16, 4); \ + DECL_VARIABLE(VAR, uint, 32, 2); \ + DECL_VARIABLE(VAR, float, 32, 2); \ + DECL_VARIABLE(VAR, int, 16, 8); \ + DECL_VARIABLE(VAR, int, 32, 4); \ + DECL_VARIABLE(VAR, uint, 16, 8); \ + DECL_VARIABLE(VAR, uint, 32, 4); \ + DECL_VARIABLE(VAR, float, 32, 4) + + /* vector_res = vmlx_lane(vector, vector2, vector3, lane), + then store the result. */ +#define TEST_VMLX_LANE1(INSN, Q, T1, T2, W, N, N2, L) \ + VECT_VAR(vector_res, T1, W, N) = \ + INSN##Q##_lane_##T2##W(VECT_VAR(vector, T1, W, N), \ + VECT_VAR(vector2, T1, W, N), \ + VECT_VAR(vector3, T1, W, N2), \ + L); \ + vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), \ + VECT_VAR(vector_res, T1, W, N)) + +#define TEST_VMLX_LANE(INSN, Q, T1, T2, W, N, N2, V) \ + TEST_VMLX_LANE1(INSN, Q, T1, T2, W, N, N2, V) + + DECL_VMLX_LANE(vector); + DECL_VMLX_LANE(vector2); + DECL_VMLX_LANE(vector_res); + + DECL_VARIABLE(vector3, int, 16, 4); + DECL_VARIABLE(vector3, int, 32, 2); + DECL_VARIABLE(vector3, uint, 16, 4); + DECL_VARIABLE(vector3, uint, 32, 2); + DECL_VARIABLE(vector3, float, 32, 2); + + clean_results (); + + VLOAD(vector, buffer, , int, s, 16, 4); + VLOAD(vector, buffer, , int, s, 32, 2); + VLOAD(vector, buffer, , uint, u, 16, 4); + VLOAD(vector, buffer, , uint, u, 32, 2); + VLOAD(vector, buffer, q, int, s, 16, 8); + VLOAD(vector, buffer, q, int, s, 32, 4); + VLOAD(vector, buffer, q, uint, u, 16, 8); + VLOAD(vector, buffer, q, uint, u, 32, 4); + VLOAD(vector, buffer, , float, f, 32, 2); + VLOAD(vector, buffer, q, float, f, 32, 4); + + VDUP(vector2, , int, s, 16, 4, 0x55); + VDUP(vector2, , int, s, 32, 2, 0x55); + VDUP(vector2, , uint, u, 16, 4, 0x55); + VDUP(vector2, , uint, u, 32, 2, 0x55); + VDUP(vector2, , float, f, 32, 2, 55.3f); + VDUP(vector2, q, int, s, 16, 8, 0x55); + VDUP(vector2, q, int, s, 32, 4, 0x55); + VDUP(vector2, q, uint, u, 16, 8, 0x55); + VDUP(vector2, q, uint, u, 32, 4, 0x55); + VDUP(vector2, q, float, f, 32, 4, 55.8f); + + VDUP(vector3, , int, s, 16, 4, 0xBB); + VDUP(vector3, , int, s, 32, 2, 0xBB); + VDUP(vector3, , uint, u, 16, 4, 0xBB); + VDUP(vector3, , uint, u, 32, 2, 0xBB); + VDUP(vector3, , float, f, 32, 2, 11.34f); + + /* Choose lane arbitrarily. */ + TEST_VMLX_LANE(INSN_NAME, , int, s, 16, 4, 4, 2); + TEST_VMLX_LANE(INSN_NAME, , int, s, 32, 2, 2, 1); + TEST_VMLX_LANE(INSN_NAME, , uint, u, 16, 4, 4, 2); + TEST_VMLX_LANE(INSN_NAME, , uint, u, 32, 2, 2, 1); + TEST_VMLX_LANE(INSN_NAME, , float, f, 32, 2, 2, 1); + TEST_VMLX_LANE(INSN_NAME, q, int, s, 16, 8, 4, 3); + TEST_VMLX_LANE(INSN_NAME, q, int, s, 32, 4, 2, 1); + TEST_VMLX_LANE(INSN_NAME, q, uint, u, 16, 8, 4, 2); + TEST_VMLX_LANE(INSN_NAME, q, uint, u, 32, 4, 2, 1); + TEST_VMLX_LANE(INSN_NAME, q, float, f, 32, 4, 2, 1); + + CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, ""); + CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, ""); + CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, ""); + CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, ""); + CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, ""); + CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, ""); + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, ""); + CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, ""); + CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, ""); + CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, ""); +} + +int main (void) +{ + FNNAME (INSN_NAME) (); + return 0; +} Index: gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_lane.c =================================================================== --- gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_lane.c (revision 0) +++ gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_lane.c (working copy) @@ -0,0 +1,23 @@ +#include <arm_neon.h> +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +#define INSN_NAME vmla +#define TEST_MSG "VMLA_LANE" + +/* Expected results. */ +VECT_VAR_DECL(expected,int,16,4) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a }; +VECT_VAR_DECL(expected,int,32,2) [] = { 0x3e07, 0x3e08 }; +VECT_VAR_DECL(expected,uint,16,4) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a }; +VECT_VAR_DECL(expected,uint,32,2) [] = { 0x3e07, 0x3e08 }; +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x4418c687, 0x44190687 }; +VECT_VAR_DECL(expected,int,16,8) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a, + 0x3e0b, 0x3e0c, 0x3e0d, 0x3e0e }; +VECT_VAR_DECL(expected,int,32,4) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a }; +VECT_VAR_DECL(expected,uint,16,8) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a, + 0x3e0b, 0x3e0c, 0x3e0d, 0x3e0e }; +VECT_VAR_DECL(expected,uint,32,4) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a }; +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x441a3168, 0x441a7168, + 0x441ab168, 0x441af168 }; + +#include "vmlX_lane.inc" Index: gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_lane.c =================================================================== --- gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_lane.c (revision 0) +++ gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_lane.c (working copy) @@ -0,0 +1,25 @@ +#include <arm_neon.h> +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +#define INSN_NAME vmls +#define TEST_MSG "VMLS_LANE" + +/* Expected results. */ +VECT_VAR_DECL(expected,int,16,4) [] = { 0xc1d9, 0xc1da, 0xc1db, 0xc1dc }; +VECT_VAR_DECL(expected,int,32,2) [] = { 0xffffc1d9, 0xffffc1da }; +VECT_VAR_DECL(expected,uint,16,4) [] = { 0xc1d9, 0xc1da, 0xc1db, 0xc1dc }; +VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffc1d9, 0xffffc1da }; +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc420c687, 0xc4208687 }; +VECT_VAR_DECL(expected,int,16,8) [] = { 0xc1d9, 0xc1da, 0xc1db, 0xc1dc, + 0xc1dd, 0xc1de, 0xc1df, 0xc1e0 }; +VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffc1d9, 0xffffc1da, + 0xffffc1db, 0xffffc1dc }; +VECT_VAR_DECL(expected,uint,16,8) [] = { 0xc1d9, 0xc1da, 0xc1db, 0xc1dc, + 0xc1dd, 0xc1de, 0xc1df, 0xc1e0 }; +VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffc1d9, 0xffffc1da, + 0xffffc1db, 0xffffc1dc }; +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc4223168, 0xc421f168, + 0xc421b168, 0xc4217168 }; + +#include "vmlX_lane.inc"