SFmode moves were using 8-bit transfers instead of 16-bit. This patch copies the SImode move pattern, which expands into 16-bit moves.
Since this only affects rl78, and the SImode code is well tested, I'm applying this now so it will be in gcc 5. * config/rl78/rl78-protos.h (rl78_split_movsi): Accept a mode as well. * config/rl78/rl78-expand.md (movsf): New, same as movsi. * config/rl78/rl78.c (rl78_split_movsi): Accept a mode, use it instead of hardcoding SImode. Index: gcc/config/rl78/rl78-protos.h =================================================================== --- gcc/config/rl78/rl78-protos.h (revision 220948) +++ gcc/config/rl78/rl78-protos.h (working copy) @@ -18,13 +18,13 @@ along with GCC; see the file COPYING3. If not see <http://www.gnu.org/licenses/>. */ void rl78_emit_eh_epilogue (rtx); void rl78_expand_compare (rtx *); void rl78_expand_movsi (rtx *); -void rl78_split_movsi (rtx *); +void rl78_split_movsi (rtx *, enum machine_mode); int rl78_force_nonfar_2 (rtx *, rtx (*gen)(rtx,rtx)); int rl78_force_nonfar_3 (rtx *, rtx (*gen)(rtx,rtx,rtx)); void rl78_expand_eh_epilogue (rtx); void rl78_expand_epilogue (void); void rl78_expand_prologue (void); int rl78_far_p (rtx x); Index: gcc/config/rl78/rl78-expand.md =================================================================== --- gcc/config/rl78/rl78-expand.md (revision 220948) +++ gcc/config/rl78/rl78-expand.md (working copy) @@ -84,13 +84,27 @@ "#" "" [(set (match_operand:HI 2 "nonimmediate_operand") (match_operand:HI 4 "general_operand")) (set (match_operand:HI 3 "nonimmediate_operand") (match_operand:HI 5 "general_operand"))] - "rl78_split_movsi (operands);" + "rl78_split_movsi (operands, SImode);" + [(set_attr "valloc" "op1")] +) + +(define_insn_and_split "movsf" + [(set (match_operand:SF 0 "nonimmediate_operand" "=vYS,v,Wfr") + (match_operand:SF 1 "general_operand" "viYS,Wfr,v"))] + "" + "#" + "" + [(set (match_operand:HI 2 "nonimmediate_operand") + (match_operand:HI 4 "general_operand")) + (set (match_operand:HI 3 "nonimmediate_operand") + (match_operand:HI 5 "general_operand"))] + "rl78_split_movsi (operands, SFmode);" [(set_attr "valloc" "op1")] ) ;;---------- Conversions ------------------------ (define_expand "zero_extendqihi2" Index: gcc/config/rl78/rl78.c =================================================================== --- gcc/config/rl78/rl78.c (revision 220948) +++ gcc/config/rl78/rl78.c (working copy) @@ -503,31 +503,31 @@ rl78_expand_movsi (rtx *operands) emit_move_insn (op02, op12); } } /* Generate code to move an SImode value. */ void -rl78_split_movsi (rtx *operands) +rl78_split_movsi (rtx *operands, enum machine_mode omode) { rtx op00, op02, op10, op12; - op00 = rl78_subreg (HImode, operands[0], SImode, 0); - op02 = rl78_subreg (HImode, operands[0], SImode, 2); + op00 = rl78_subreg (HImode, operands[0], omode, 0); + op02 = rl78_subreg (HImode, operands[0], omode, 2); if (GET_CODE (operands[1]) == CONST || GET_CODE (operands[1]) == SYMBOL_REF) { op10 = gen_rtx_ZERO_EXTRACT (HImode, operands[1], GEN_INT (16), GEN_INT (0)); op10 = gen_rtx_CONST (HImode, op10); op12 = gen_rtx_ZERO_EXTRACT (HImode, operands[1], GEN_INT (16), GEN_INT (16)); op12 = gen_rtx_CONST (HImode, op12); } else { - op10 = rl78_subreg (HImode, operands[1], SImode, 0); - op12 = rl78_subreg (HImode, operands[1], SImode, 2); + op10 = rl78_subreg (HImode, operands[1], omode, 0); + op12 = rl78_subreg (HImode, operands[1], omode, 2); } if (rtx_equal_p (operands[0], operands[1])) ; else if (rtx_equal_p (op00, op12)) {