Hello! 2015-04-13 Uros Bizjak <ubiz...@gmail.com>
* config/i386/i386.md (*bmi2_umul<mode><dwi>3_1): Merge from *bmi2_umulsidi3_1 and *bmi2_umulditi3_1 using DWIH mode iterator. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}, committed to mainline. Uros.
Index: i386.md =================================================================== --- i386.md (revision 221840) +++ i386.md (working copy) @@ -6818,42 +6818,24 @@ (clobber (reg:CC FLAGS_REG))])] "TARGET_QIMODE_MATH") -(define_insn "*bmi2_umulditi3_1" - [(set (match_operand:DI 0 "register_operand" "=r") - (mult:DI - (match_operand:DI 2 "nonimmediate_operand" "%d") - (match_operand:DI 3 "nonimmediate_operand" "rm"))) - (set (match_operand:DI 1 "register_operand" "=r") - (truncate:DI - (lshiftrt:TI - (mult:TI (zero_extend:TI (match_dup 2)) - (zero_extend:TI (match_dup 3))) - (const_int 64))))] - "TARGET_64BIT && TARGET_BMI2 +(define_insn "*bmi2_umul<mode><dwi>3_1" + [(set (match_operand:DWIH 0 "register_operand" "=r") + (mult:DWIH + (match_operand:DWIH 2 "nonimmediate_operand" "%d") + (match_operand:DWIH 3 "nonimmediate_operand" "rm"))) + (set (match_operand:DWIH 1 "register_operand" "=r") + (truncate:DWIH + (lshiftrt:<DWI> + (mult:<DWI> (zero_extend:<DWI> (match_dup 2)) + (zero_extend:<DWI> (match_dup 3))) + (match_operand:QI 4 "const_int_operand" "n"))))] + "TARGET_BMI2 && INTVAL (operands[4]) == <MODE_SIZE> * BITS_PER_UNIT && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "mulx\t{%3, %0, %1|%1, %0, %3}" [(set_attr "type" "imulx") (set_attr "prefix" "vex") - (set_attr "mode" "DI")]) + (set_attr "mode" "<MODE>")]) -(define_insn "*bmi2_umulsidi3_1" - [(set (match_operand:SI 0 "register_operand" "=r") - (mult:SI - (match_operand:SI 2 "nonimmediate_operand" "%d") - (match_operand:SI 3 "nonimmediate_operand" "rm"))) - (set (match_operand:SI 1 "register_operand" "=r") - (truncate:SI - (lshiftrt:DI - (mult:DI (zero_extend:DI (match_dup 2)) - (zero_extend:DI (match_dup 3))) - (const_int 32))))] - "!TARGET_64BIT && TARGET_BMI2 - && !(MEM_P (operands[1]) && MEM_P (operands[2]))" - "mulx\t{%3, %0, %1|%1, %0, %3}" - [(set_attr "type" "imulx") - (set_attr "prefix" "vex") - (set_attr "mode" "SI")]) - (define_insn "*umul<mode><dwi>3_1" [(set (match_operand:<DWI> 0 "register_operand" "=r,A") (mult:<DWI> @@ -6902,7 +6884,7 @@ { split_double_mode (<DWI>mode, &operands[0], 1, &operands[3], &operands[4]); - operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)); + operands[5] = GEN_INT (<MODE_SIZE> * BITS_PER_UNIT); }) (define_insn "*mul<mode><dwi>3_1"