On 16/04/15 00:00, Kugan wrote:
>
>
> On 16/04/15 08:32, Jakub Jelinek wrote:
>> On Thu, Apr 16, 2015 at 08:27:24AM +1000, Kugan wrote:
>>> + if (<CODE> == LSHIFTRT)
>>> + {
>>> + emit_insn (gen_aarch64_lshr_sisd_or_int_<mode>3 (operands[0],
>>> operands[1], operands[2]));
>>
>> That is way too long line, please wrap it.
>>
>>> + DONE;
>>> + }
>>> }
>>> )
>>>
>>> @@ -3361,11 +3367,12 @@
>>> )
>>>
>>> ;; Logical right shift using SISD or Integer instruction
>>> -(define_insn "*aarch64_lshr_sisd_or_int_<mode>3"
>>> - [(set (match_operand:GPI 0 "register_operand" "=w,&w,r")
>>> +(define_insn "aarch64_lshr_sisd_or_int_<mode>3"
>>> + [(set (match_operand:GPI 0 "register_operand" "=w,w,r")
>>> (lshiftrt:GPI
>>> (match_operand:GPI 1 "register_operand" "w,w,r")
>>> - (match_operand:QI 2 "aarch64_reg_or_shift_imm_<mode>"
>>> "Us<cmode>,w,rUs<cmode>")))]
>>> + (match_operand:QI 2 "aarch64_reg_or_shift_imm_<mode>"
>>> "Us<cmode>,w,rUs<cmode>")))
>>
>> Though, this one too...
>>
>
> Fixed in the attached patch.
>
> Thanks,
> Kugan
>
Not ok.
You need to ensure that your scratch register cannot overlap op1, since
the scratch is written before op1 is read.
R.
