On Wed, 2015-04-22 at 17:16 -0500, Segher Boessenkool wrote: > On Wed, Apr 22, 2015 at 08:43:10AM -0500, Peter Bergner wrote: > > > Maybe you can fold tabortdc with tabortwc now? Use one UNSPEC name > > > for both, :GPR and <wd>? > > > > Wouldn't that change the tabortwc pattern to use DImode rather > > than SImode when compiled with -m64 or -m32 -mpowerpc64? > > I'm not sure we want that. > > The GPR mode iterator creates two patterns, one for SI and one for DI, > and the tabortwc would be the one for SI if you use <wd>.
Ah, I think I know what you mean. Sure, I can try that, > > > > + case HTM_BUILTIN_TTEST: /* Alias for: tabortwci. 0,r0,0 */ > > > > + op[nopnds++] = GEN_INT (0); > > > > + op[nopnds++] = gen_rtx_REG (SImode, 0); > > > > + op[nopnds++] = GEN_INT (0); > > > > > > Is that really r0, isn't that (0|rA)? [Too lazy to read the docs myself > > > right now, sorry.] > > > > The ISA doc shows: > > [snip] > > Thanks for looking it up! > > I'm still a bit worried about putting a reg in the RTL (while the instruction > doesn't actually use one), but perhaps it's harmless. I'm not sure what you mean by the "instruction doesn't use one". The hardware instruction does use a register for its second operand (even though its contents are ignored due to TO == 0) and the pattern requires us to pass in a reg rtx, so I'm not sure what you're referring to. > >> This skips this test on -m32 -mpowerpc64, is that on purpose? > > > > Ummm, not exactly. :-) Not that many people test that though. > > I'll see if I can find a replacement for lp64 that covers that case. > > Maybe just { powerpc64 } works? I'll take a look at that to see if that works, thanks. Peter