> > I've renamed EXT_SSE_REG_P into EXT_REX_SSE_REG_P for consistency.
> > Ok for stage1?
> Patch is OK for stage1.
>
> --
> Thanks, K
>
>
> > On 19 Mar 12:24, Ilya Tocar wrote:
> > > Hi,
> > >
> > > There were some discussion about "x" constraints being too conservative
> > > for some patterns in i386.md.
> > > Patch below fixes it. This is probably stage1 material.
> > >
> > > ChangeLog:
> > >
> > > gcc/
> > >
> > 2015-03-23 Ilya Tocar <ilya.to...@intel.com>
> >
> > * config/i386/i386.h (EXT_REX_SSE_REG_P): New.
> > * config/i386/i386.md (*cmpi<FPCMP:unord><MODEF:mode>_mixed): Use "v"
> > constraint.
> > (*cmpi<FPCMP:unord><MODEF:mode>_sse): Ditto.
> > (*movxi_internal_avx512f): Ditto.
> > (define_split): Check for xmm16+, when splitting scalar float_extend.
> > (*extendsfdf2_mixed): Use "v" constraint.
> > (*extendsfdf2_sse): Ditto.
> > (define_split): Check for xmm16+, when splitting scalar float_truncate.
> > (*truncdfsf_fast_sse): Use "v" constraint.
> > (fix_trunc<MODEF:mode><SWI48:mode>_sse): Ditto.
> > (*float<SWI48:mode><MODEF:mode>2_sse): Ditto.
> > (define_peephole2): Check for xmm16+, when converting scalar
> > float_truncate.
> > (define_peephole2): Check for xmm16+, when converting scalar
> > float_extend.
> > (*fop_<mode>_comm_mixed): Use "v" constraint.
> > (*fop_<mode>_comm_sse): Ditto.
> > (*fop_<mode>_1_mixed): Ditto.
> > (*sqrt<mode>2_sse): Ditto.
> > (*ieee_s<ieee_maxmin><mode>3): Ditto.
> >
> >
Hi,
Looks like I missed some splits, which caused PR65915.
Patch below fixes it.
Ok for trunk?
2015-04-28 Ilya Tocar <ilya.to...@intel.com>
* config/i386/i386.md (define_split): Check for xmm16+,
when splitting scalar float conversion.
---
gcc/config/i386/i386.md | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 937871a..af1cd9b 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -4897,7 +4897,9 @@
"TARGET_SSE2 && TARGET_SSE_MATH
&& TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
&& reload_completed && SSE_REG_P (operands[0])
- && (MEM_P (operands[1]) || TARGET_INTER_UNIT_MOVES_TO_VEC)"
+ && (MEM_P (operands[1]) || TARGET_INTER_UNIT_MOVES_TO_VEC)
+ && (!EXT_REX_SSE_REG_P (operands[0])
+ || TARGET_AVX512VL)"
[(const_int 0)]
{
operands[3] = simplify_gen_subreg (<ssevecmode>mode, operands[0],
@@ -4921,7 +4923,9 @@
"TARGET_SSE2 && TARGET_SSE_MATH
&& TARGET_SSE_PARTIAL_REG_DEPENDENCY
&& optimize_function_for_speed_p (cfun)
- && reload_completed && SSE_REG_P (operands[0])"
+ && reload_completed && SSE_REG_P (operands[0])
+ && (!EXT_REX_SSE_REG_P (operands[0])
+ || TARGET_AVX512VL)"
[(const_int 0)]
{
const machine_mode vmode = <MODEF:ssevecmode>mode;
--
1.8.3.1
