On Wed, Aug 5, 2015 at 10:07 AM, Kirill Yukhin <kirill.yuk...@gmail.com> wrote: > Hello, > > Is it ok to backport the patch to gcc-5-branch?
A minor attribute fix is needed, please update type attribute of *vec_concatv2df for added alternatives, also for mainline. Otherwise, the patch looks safe, so OK for backport after a couple of days. Thanks, Uros. > -- > Thanks, K > >> On 04 Aug 15:31, Kirill Yukhin wrote: >> >> commit 1055739cb51648794a01afd85f59efadd14378ed >> Author: Kirill Yukhin <kirill.yuk...@intel.com> >> Date: Mon Aug 3 15:21:06 2015 +0300 >> >> Fix vec_concatv2df and vec_dupv2df to block wrongly enabled AVX-512VL >> insns. >> >> diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md >> index 5c5c1fc..9ffe9aa 100644 >> --- a/gcc/config/i386/i386.md >> +++ b/gcc/config/i386/i386.md >> @@ -784,7 +784,8 @@ >> (define_attr "isa" "base,x64,x64_sse4,x64_sse4_noavx,x64_avx,nox64, >> sse2,sse2_noavx,sse3,sse4,sse4_noavx,avx,noavx, >> avx2,noavx2,bmi,bmi2,fma4,fma,avx512f,noavx512f, >> - fma_avx512f,avx512bw,noavx512bw,avx512dq,noavx512dq" >> + fma_avx512f,avx512bw,noavx512bw,avx512dq,noavx512dq, >> + avx512vl,noavx512vl" >> (const_string "base")) >> >> (define_attr "enabled" "" >> @@ -819,6 +820,8 @@ >> (eq_attr "isa" "noavx512bw") (symbol_ref "!TARGET_AVX512BW") >> (eq_attr "isa" "avx512dq") (symbol_ref "TARGET_AVX512DQ") >> (eq_attr "isa" "noavx512dq") (symbol_ref "!TARGET_AVX512DQ") >> + (eq_attr "isa" "avx512vl") (symbol_ref "TARGET_AVX512VL") >> + (eq_attr "isa" "noavx512vl") (symbol_ref "!TARGET_AVX512VL") >> ] >> (const_int 1))) >> >> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md >> index 0970f0e..ca1ec2e 100644 >> --- a/gcc/config/i386/sse.md >> +++ b/gcc/config/i386/sse.md >> @@ -8638,44 +8638,50 @@ >> (set_attr "mode" "DF,DF,V1DF,V1DF,V1DF,V2DF,V1DF,V1DF,V1DF")]) >> >> (define_insn "vec_dupv2df<mask_name>" >> - [(set (match_operand:V2DF 0 "register_operand" "=x,v") >> + [(set (match_operand:V2DF 0 "register_operand" "=x,x,v") >> (vec_duplicate:V2DF >> - (match_operand:DF 1 "nonimmediate_operand" " 0,vm")))] >> + (match_operand:DF 1 "nonimmediate_operand" " 0,xm,vm")))] >> "TARGET_SSE2 && <mask_avx512vl_condition>" >> "@ >> unpcklpd\t%0, %0 >> - %vmovddup\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}" >> - [(set_attr "isa" "noavx,sse3") >> + %vmovddup\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1} >> + vmovddup\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}" >> + [(set_attr "isa" "noavx,sse3,avx512vl") >> (set_attr "type" "sselog1") >> - (set_attr "prefix" "orig,maybe_vex") >> - (set_attr "mode" "V2DF,DF")]) >> + (set_attr "prefix" "orig,maybe_vex,evex") >> + (set_attr "mode" "V2DF,DF,DF")]) >> >> (define_insn "*vec_concatv2df" >> - [(set (match_operand:V2DF 0 "register_operand" "=x,v,v,x,x,v,x,x") >> + [(set (match_operand:V2DF 0 "register_operand" "=x,x,v,x,v,x,x,v,x,x") >> (vec_concat:V2DF >> - (match_operand:DF 1 "nonimmediate_operand" " 0,v,m,0,x,m,0,0") >> - (match_operand:DF 2 "vector_move_operand" " x,v,1,m,m,C,x,m")))] >> + (match_operand:DF 1 "nonimmediate_operand" " 0,x,v,m,m,0,x,m,0,0") >> + (match_operand:DF 2 "vector_move_operand" " x,x,v,1,1,m,m,C,x,m")))] >> "TARGET_SSE >> && (!(MEM_P (operands[1]) && MEM_P (operands[2])) >> || (TARGET_SSE3 && rtx_equal_p (operands[1], operands[2])))" >> "@ >> unpcklpd\t{%2, %0|%0, %2} >> vunpcklpd\t{%2, %1, %0|%0, %1, %2} >> + vunpcklpd\t{%2, %1, %0|%0, %1, %2} >> %vmovddup\t{%1, %0|%0, %1} >> + vmovddup\t{%1, %0|%0, %1} >> movhpd\t{%2, %0|%0, %2} >> vmovhpd\t{%2, %1, %0|%0, %1, %2} >> %vmovsd\t{%1, %0|%0, %1} >> movlhps\t{%2, %0|%0, %2} >> movhps\t{%2, %0|%0, %2}" >> - [(set_attr "isa" "sse2_noavx,avx,sse3,sse2_noavx,avx,sse2,noavx,noavx") >> + [(set_attr "isa" >> "sse2_noavx,avx,avx512vl,sse3,avx512vl,sse2_noavx,avx,sse2,noavx,noavx") >> (set (attr "type") >> (if_then_else >> (eq_attr "alternative" "0,1,2") >> (const_string "sselog") >> (const_string "ssemov"))) >> - (set_attr "prefix_data16" "*,*,*,1,*,*,*,*") >> - (set_attr "prefix" "orig,vex,maybe_vex,orig,vex,maybe_vex,orig,orig") >> - (set_attr "mode" "V2DF,V2DF,DF,V1DF,V1DF,DF,V4SF,V2SF")]) >> + (set (attr "prefix_data16") >> + (if_then_else (eq_attr "alternative" "5") >> + (const_string "1") >> + (const_string "*"))) >> + (set_attr "prefix" >> "orig,vex,evex,maybe_vex,evex,orig,vex,maybe_vex,orig,orig") >> + (set_attr "mode" "V2DF,V2DF,V2DF, DF, DF, V1DF,V1DF,DF,V4SF,V2SF")]) >> >> ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; >> ;;