On Tue, Jun 02, 2015 at 05:32:02PM +0200, Andreas Krebbel wrote:
...
> +(define_insn "*<shift><mode>3_imm"
> + [(set (match_operand:GPR 0 "register_operand" "=d")
> + (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
> + (match_operand 2 "immediate_operand" "J")))]
> + ""
> + "s<lr>l<g>\t%0,<1>%2"
> + [(set_attr "op_type" "RS<E>")
> + (set_attr "atype" "reg")])
> +
> +(define_insn "*<shift><mode>3_immreg"
> + [(set (match_operand:GPR 0 "register_operand" "=d")
> + (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
> + (plus:SI
> + (match_operand:SI 2 "register_operand" "a")
> + (match_operand 3 "immediate_operand" "J"))))]
> + ""
> + "s<lr>l<g>\t%0,<1>%2(%3)"
> [(set_attr "op_type" "RS<E>")
> (set_attr "atype" "reg")])
>
>
> With this we still get:
>
> shift:
> sll %r2,%r3(3)
> llgfr %r2,%r2
> br %r14
>
> for:
>
> unsigned int
> shift (unsigned int s, unsigned int a)
> {
> return s << (a + 3);
> }
>
> I'm still hoping for a better idea though ...
I've implemented it differently now. Regarding generated code it is
not perfect but its the I have so far. Further ideas are welcome.
[PATCH] S/390: Disallow SImode addresses in 64 bit
https://gcc.gnu.org/ml/gcc-patches/2015-08/msg00346.html
Bye,
-Andreas-
