Hi All, Here is patch which contains (1) modifying of core2.md to conform Haswell pipeline and adding of missed instruction reservation for instructions with vector operands. (2) increase reassociation width for float-point operations for Haswell family and 64-bit target, this allows to get +10% speedup on spec2006/410.bwaves for Skylake processor.
Bootstrap and regression testing did not show any new failures. Is it OK for trunk? ChangeLog: 2015-08-14 Yuri Rumyantsev <ysrum...@gmail.com> * config/i386/core2.md: Confrom instruction reservation to Haswell pipeline. * config/i386/i386.c (ix86_reassociation_width): Increase reassociation width for float-point operations.
hsw.patch
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