The V_THREE_ELEM attribute used BLKmode for most sizes, but occasionally
EImode. This patch changes to BLKmode in all cases, explicitly setting
memory size (thus, preserving size for the cases that were EImode, and
setting size for the first time for cases that were already BLKmode).
The patterns affected are only for intrinsics: the aarch64_ld3r
expanders and aarch64_simd_ld3r insns, and the
aarch64_vec_{load,store}_lanesci_lane insns used by the
aarch64_{ld,st}3_lane expanders.
bootstrapped and check-gcc on aarch64-none-linux-gnu
gcc/ChangeLog:
* config/aarch64/aarch64-simd.md (aarch64_simd_ld3r<mode>,
aarch64_vec_load_lanesci_lane<mode>,
aarch64_vec_store_lanesci_lane<mode>): Change operand mode
from <V_THREE_ELEM> to BLK.
(aarch64_ld3r<mode>, aarch64_ld3_lane<mode>,
aarch64_st3_lane<VQ:mode>): Generate MEM rtx with BLKmode, call
set_mem_size.
* config/aarch64/iterators.md (V_THREE_ELEM): Remove.
---
gcc/config/aarch64/aarch64-simd.md | 27 ++++++++++++++-------------
gcc/config/aarch64/iterators.md | 8 --------
2 files changed, 14 insertions(+), 21 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-simd.md
b/gcc/config/aarch64/aarch64-simd.md
index 7b7a1b8..156fc4f 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -4001,7 +4001,7 @@
(define_insn "aarch64_simd_ld3r<mode>"
[(set (match_operand:CI 0 "register_operand" "=w")
- (unspec:CI [(match_operand:<V_THREE_ELEM> 1
"aarch64_simd_struct_operand" "Utv")
+ (unspec:CI [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")
(unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) ]
UNSPEC_LD3_DUP))]
"TARGET_SIMD"
@@ -4011,7 +4011,7 @@
(define_insn "aarch64_vec_load_lanesci_lane<mode>"
[(set (match_operand:CI 0 "register_operand" "=w")
- (unspec:CI [(match_operand:<V_THREE_ELEM> 1
"aarch64_simd_struct_operand" "Utv")
+ (unspec:CI [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")
(match_operand:CI 2 "register_operand" "0")
(match_operand:SI 3 "immediate_operand" "i")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
@@ -4052,11 +4052,11 @@
;; RTL uses GCC vector extension indices, so flip only for assembly.
(define_insn "aarch64_vec_store_lanesci_lane<mode>"
- [(set (match_operand:<V_THREE_ELEM> 0 "aarch64_simd_struct_operand" "=Utv")
- (unspec:<V_THREE_ELEM> [(match_operand:CI 1 "register_operand" "w")
- (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
- (match_operand:SI 2 "immediate_operand" "i")]
- UNSPEC_ST3_LANE))]
+ [(set (match_operand:BLK 0 "aarch64_simd_struct_operand" "=Utv")
+ (unspec:BLK [(match_operand:CI 1 "register_operand" "w")
+ (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
+ (match_operand:SI 2 "immediate_operand" "i")]
+ UNSPEC_ST3_LANE))]
"TARGET_SIMD"
{
operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
@@ -4368,8 +4368,8 @@
(unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
"TARGET_SIMD"
{
- machine_mode mode = <V_THREE_ELEM>mode;
- rtx mem = gen_rtx_MEM (mode, operands[1]);
+ rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
+ set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) * 3);
emit_insn (gen_aarch64_simd_ld3r<mode> (operands[0], mem));
DONE;
@@ -4589,8 +4589,8 @@
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
"TARGET_SIMD"
{
- machine_mode mode = <V_THREE_ELEM>mode;
- rtx mem = gen_rtx_MEM (mode, operands[1]);
+ rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
+ set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) * 3);
aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCONQ>mode),
NULL);
@@ -4874,8 +4874,9 @@
(match_operand:SI 2 "immediate_operand")]
"TARGET_SIMD"
{
- machine_mode mode = <V_THREE_ELEM>mode;
- rtx mem = gen_rtx_MEM (mode, operands[0]);
+ rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
+ set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) * 3);
+
operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
emit_insn (gen_aarch64_vec_store_lanesci_lane<VQ:mode> (mem,
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 98b6714..ae0be0b 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -568,14 +568,6 @@
(V2SF "V2SF") (V4SF "V2SF")
(DF "V2DI") (V2DF "V2DI")])
-;; Similar, for three elements.
-(define_mode_attr V_THREE_ELEM [(V8QI "BLK") (V16QI "BLK")
- (V4HI "BLK") (V8HI "BLK")
- (V2SI "BLK") (V4SI "BLK")
- (DI "EI") (V2DI "EI")
- (V2SF "BLK") (V4SF "BLK")
- (DF "EI") (V2DF "EI")])
-
;; Similar, for four elements.
(define_mode_attr V_FOUR_ELEM [(V8QI "SI") (V16QI "SI")
(V4HI "V4HI") (V8HI "V4HI")
--
1.8.3
