On Thu, Sep 17, 2015 at 9:54 AM, Matthew Wahab <matthew.wa...@foss.arm.com> wrote: > Hello, > > ARMv8.1 adds atomic swap and atomic load-operate instructions with > optional memory ordering specifiers. This patch uses the ARMv8.1 > load-operate instructions to implement the atomic_<op>_fetch patterns. > > The approach is to use the atomic load-operate instruction to atomically > load the data and update memory and then to use the loaded data to > calculate the value that the instruction would have stored. The > calculation attempts to mirror the operation of the atomic instruction. > For example, atomic_and_fetch<mode> is implemented with an atomic > load-bic so the result is also calculated using a BIC instruction. > > The general form of the code generated for an atomic_<op>_fetch, with > destination D, source S, memory address A and memory order MO, depends > on whether or not the operation is directly supported by the > instruction. If <op> is one of PLUS, IOR or XOR, the code generated is: > > ld<opc><mo><sz> S, D, [A] > <inst> D, D, S > where > <opc> is one {add, set, eor} > <inst> is one of {add, orr, xor} > <mo> is one of {'', 'a', 'l', 'al'} depending on memory order MO. > <sz> is one of {'', 'b', 'h'} depending on the data size. > > If <op> is SUB, the code generated is: > > neg S, S > ldadd<mo><sz> S, D, [A] > add D, D, S > > If <op> is AND, the code generated is: > > not S, S > ldclr<mo><sz> S, D, [A] > bic D, S, S > > Any operation not in {PLUS, IOR, XOR, SUB, AND} is passed to the > existing aarch64_split_atomic_op function, to implement the operation > using sequences built with the ARMv8 load-exclusive/store-exclusive > instructions > > Tested the series for aarch64-none-linux-gnu with native bootstrap and > make check. Also tested for aarch64-none-elf with cross-compiled > check-gcc on an ARMv8.1 emulator with +lse enabled by default.
Are you going to add some builtins for MIN/MAX support too? Thanks, Andrew Pinski > > Ok for trunk? > Matthew > > 2015-09-17 Matthew Wahab <matthew.wa...@arm.com> > > * config/aarch64/aarch64-protos.h (aarch64_gen_atomic_ldop): > Adjust declaration. > * config/aarch64/aarch64.c (aarch64_emit_bic): New. > (aarch64_gen_atomic_load_op): Adjust comment. Add parameter > out_result. Update to support update-fetch operations. > * config/aarch64/atomics.md (aarch64_atomic_exchange<mode>_lse): > Adjust for change to aarch64_gen_atomic_ldop. > (aarch64_atomic_<atomic_optab><mode>_lse): Likewise. > (aarch64_atomic_fetch_<atomic_optab><mode>_lse): Likewise. > (atomic_<atomic_optab>_fetch<mode>): Change to an expander. > (aarch64_atomic_<atomic_optab>_fetch<mode>): New. > (aarch64_atomic_<atomic_optab>_fetch<mode>_lse): New. > > gcc/testsuite > 2015-09-17 Matthew Wahab <matthew.wa...@arm.com> > > * gcc.target/aarch64/atomic-inst-ldadd.c: Add tests for > update-fetch operations. > * gcc.target/aarch64/atomic-inst-ldlogic.c: Likewise. >