On Wed, Nov 11, 2015 at 6:34 PM, Jim Wilson <jim.wil...@linaro.org> wrote: > This adds an option for the Qualcomm server parts, qdf24xx, just > optimizing like a cortex-a57 for now, same as how the initial Samsung > exynos-m1 support worked. > > This was tested with armv8 and aarch64 bootstraps and make check. > > I had to disable the cortex-a57 fma steering pass in the aarch64 port > while testing the patch. A bootstrap for aarch64 configured > --with-cpu=cortex-a57 gives multiple ICEs while building the stage1 > libstdc++. The ICEs are in scan_rtx_reg at regrename.c:1074. This > looks vaguely similar to PR 66785. > > I am also seeing extra make check failures due to ICEs with armv8 > bootstrap builds configured --with-cpu=cortex-a57, I see ICEs in > scan_rtx_reg in regrename, and ICEs in decompose_normal_address in > rtlanal.c.
The failures are due to the usual madness in the last week of stage1. > The arm port doesn't have the fma steering support, which > seems odd, and is maybe a bug, so it isn't clear what is causing this > problem. The ARM port does not require this. The FMA steering issue is only relevant in AArch64 ISA state. > > I plan to look at these aarch64 and armv8 failures next, including PR > 66785. None of these have anything to do with my patch, as they > trigger for cortex-a57 which is already supported. This is OK to go in with a follow up to handle this cpu in t-aprofile similar to the other cpus in there - for bonus points please deal with the exynos core at the same time if not already done. regards Ramana > > Jim
