On Fri, Nov 20, 2015 at 6:47 PM, Michael Meissner <meiss...@linux.vnet.ibm.com> wrote: > On Fri, Oct 02, 2015 at 02:04:48PM -0500, Peter Bergner wrote: >> PR67808 exposes a problem with the constraints in the *extenddftf2_internal >> pattern, in that it allows TFmode operands to occupy Altivec registers >> which they are not allowed to do. Reload was able to work around the >> problem, but LRA is more pedantic and it caused it to go into an infinite >> spill loop until it ICEd. The following patch from Mike changes the TFmode >> output operand to use the "d" constraint instead of "ws". It also allows >> using the "ws" constraint for the two input operands, since that is allowed >> for DFmode operands. >> >> This passed bootstraps (with reload on by default and lra on by default) >> and shows no testsuite regressions. Is this ok for trunk? >> >> The bug is also present in the FSF 5 branch (4.9 is ok), is this ok for >> that too, assuming my bootstrap/regtesting there are clean? > > The following patch backports the fix to GCC 5.x. There were no regressions > in > doing the bootstrap/make check on both a big endian power7 system and a little > endian power8 system. Is it ok to apply the patch to the gcc-5 branch? > > 2015-10-20 Michael Meissner <meiss...@linux.vnet.ibm.com> > > Back port from trunk: > 2015-10-05 Michael Meissner <meiss...@linux.vnet.ibm.com> > Peter Bergner <berg...@vnet.ibm.com> > > PR target/67808 > * config/rs6000/rs6000.md (extenddftf2): In the expander, only > allow registers, but provide insns for the combiner to create for > loads from memory. Separate VSX code from non-VSX code. For > non-VSX code, combine extenddftf2_fprs into extenddftf2 and rename > externaldftf2_internal to externaldftf2_fprs. Reorder constraints > so that registers come before memory operations. Drop support from > converting DFmode to TFmode, if the DFmode value is in a GPR > register. > (extenddftf2_fprs): Likewise. > (extenddftf2_internal): Likewise. > (extenddftf2_vsx): Likewise. > (extendsftf2): In the expander, only allow registers, but provide > insns for the combiner to create for stores and loads.
Okay. Thanks, David
