v2 of the patch. Seems to pass the GCC testsuite, although the testsuite doesn't stress FP.
There is something wrong with current VSX SFmode constraints. Index: rs6000.md =================================================================== --- rs6000.md (revision 230723) +++ rs6000.md (working copy) @@ -77,6 +77,7 @@ UNSPEC_FRIN UNSPEC_FRIP UNSPEC_FRIZ + UNSPEC_XSRDPI UNSPEC_LD_MPIC ; load_macho_picbase UNSPEC_RELD_MPIC ; re-load_macho_picbase UNSPEC_MPIC_CORRECT ; macho_correct_pic @@ -5500,6 +5501,27 @@ [(set_attr "type" "fp") (set_attr "fp_type" "fp_addsub_<Fs>")]) +(define_insn "*xsrdpi<mode>2" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=wa") + (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "wa")] + UNSPEC_XSRDPI))] + "TARGET_<MODE>_FPR && TARGET_POPCNTD" + "xsrdpi %x0,%x1" + [(set_attr "type" "fp") + (set_attr "fp_type" "fp_addsub_<Fs>")]) + +(define_expand "lround<mode>di2" + [(set (match_dup 2) + (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "wa")] + UNSPEC_XSRDPI)) + (set (match_operand:DI 0 "gpc_reg_operand" "=d") + (unspec:DI [(match_dup 2)] + UNSPEC_FCTID))] + "TARGET_<MODE>_FPR && TARGET_POPCNTD" +{ + operands[2] = gen_reg_rtx (<MODE>mode); +}) + ; An UNSPEC is used so we don't have to support SImode in FP registers. (define_insn "stfiwx" [(set (match_operand:SI 0 "memory_operand" "=Z")