Ping.
https://gcc.gnu.org/ml/gcc-patches/2015-12/msg00526.html
Thanks,
Kyrill
On 04/12/15 09:30, Kyrill Tkachov wrote:
Hi all,
We don't handle properly the patterns for the [us]bfiz and [us]bfx instructions
when they
have an extend+ashift form. For example, the
*<ANY_EXTEND:optab><GPI:mode>_ashl<SHORT:mode> pattern.
This leads to rtx costs recuring into the extend and assigning a cost to these
patterns that is too
large.
This patch fixes that oversight.
I stumbled across this when working on a different combine patch and ended up
matching the above
pattern, only to have it rejected for -mcpu=cortex-a53 due to the erroneous
cost.
Bootstrapped and tested on aarch64.
Ok for trunk?
Thanks,
Kyrill
2015-12-04 Kyrylo Tkachov <kyrylo.tkac...@arm.com>
* config/aarch64/aarch64.c (aarch64_extend_bitfield_pattern_p):
New function.
(aarch64_rtx_costs, ZERO_EXTEND, SIGN_EXTEND cases): Use the above
to handle extend+shift rtxes.
