Here's an updated version, also covering the min/max patterns I missed before.
I've now managed to do some testing with a stage 1 compiler, by compiling all
tests in gcc.dg/vect at -O2 -ftree-vectorize -mips3d -march=mips64r2 -mabi=n32
$x -ffast-math -ffinite-math-only.
There were no changes in which files compiled (871 did, some did not due to
libraries etc. missing in my stage 1 compiler), and no changes in any assembly
output. The patterns were triggered on:
fast-math-vect-reduc-5.c, fast-math-vect-reduc-8.c, fast-math-vect-reduc-9.c,
no-fast-math-vect16.c, pr66142.c, vect-outer-fir-big-array.c, vect-outer-fir.c,
vect-outer-fir-lb-big-array.c, vect-outer-fir-lb.c, vect-reduc-10.c,
vect-reduc-6.c
I realize this is not completely representative of a 'proper' test run, in
which different files are compiled with different options, but it provides
reasonable confidence that I'm not changing any code generation.
OK for trunk? (stage 3?)
Cheers, Alan
gcc/ChangeLog:
* config/mips/mips-ps-3d.md (reduc_splus_v2sf): Remove.
(reduc_plus_scal_v2sf): New.
(reduc_smax_v2sf): Rename to...
(reduc_smax_scal_v2sf): ...here, make result SFmode, add vec_extract.
(reduc_smin_v2sf): Rename to...
(reduc_smin_scal_v2sf): ...here, make result SFmode, add vec_extract.
---
gcc/config/mips/mips-ps-3d.md | 34 ++++++++++++++++++++++------------
1 file changed, 22 insertions(+), 12 deletions(-)
diff --git a/gcc/config/mips/mips-ps-3d.md b/gcc/config/mips/mips-ps-3d.md
index 8bc7608..a93a2b9 100644
--- a/gcc/config/mips/mips-ps-3d.md
+++ b/gcc/config/mips/mips-ps-3d.md
@@ -371,13 +371,17 @@
[(set_attr "type" "fadd")
(set_attr "mode" "SF")])
-(define_insn "reduc_splus_v2sf"
- [(set (match_operand:V2SF 0 "register_operand" "=f")
- (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")
- (match_dup 1)]
- UNSPEC_ADDR_PS))]
+(define_expand "reduc_plus_scal_v2sf"
+ [(match_operand:SF 0 "register_operand" "=f")
+ (match_operand:V2SF 1 "register_operand" "f")]
"TARGET_HARD_FLOAT && TARGET_MIPS3D"
- "")
+ {
+ rtx temp = gen_reg_rtx (V2SFmode);
+ emit_insn (gen_mips_addr_ps (temp, operands[1], operands[1]));
+ rtx lane = BYTES_BIG_ENDIAN ? const1_rtx : const0_rtx;
+ emit_insn (gen_vec_extractv2sf (operands[0], temp, lane));
+ DONE;
+ })
; cvt.pw.ps - Floating Point Convert Paired Single to Paired Word
(define_insn "mips_cvt_pw_ps"
@@ -745,20 +749,26 @@
DONE;
})
-(define_expand "reduc_smin_v2sf"
- [(match_operand:V2SF 0 "register_operand")
+(define_expand "reduc_smin_scal_v2sf"
+ [(match_operand:SF 0 "register_operand")
(match_operand:V2SF 1 "register_operand")]
"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
{
- mips_expand_vec_reduc (operands[0], operands[1], gen_sminv2sf3);
+ rtx temp = gen_reg_rtx (V2SFmode);
+ mips_expand_vec_reduc (temp, operands[1], gen_sminv2sf3);
+ rtx lane = BYTES_BIG_ENDIAN ? const1_rtx : const0_rtx;
+ emit_insn (gen_vec_extractv2sf (operands[0], temp, lane));
DONE;
})
-(define_expand "reduc_smax_v2sf"
- [(match_operand:V2SF 0 "register_operand")
+(define_expand "reduc_smax_scal_v2sf"
+ [(match_operand:SF 0 "register_operand")
(match_operand:V2SF 1 "register_operand")]
"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
{
- mips_expand_vec_reduc (operands[0], operands[1], gen_smaxv2sf3);
+ rtx temp = gen_reg_rtx (V2SFmode);
+ mips_expand_vec_reduc (temp, operands[1], gen_smaxv2sf3);
+ rtx lane = BYTES_BIG_ENDIAN ? const1_rtx : const0_rtx;
+ emit_insn (gen_vec_extractv2sf (operands[0], temp, lane));
DONE;
})
--
1.9.1
