It was checked in by HJ http://gcc.gnu.org/viewcvs?view=revision&revision=177876
I am testing next patch. Thanks, K On Thu, Aug 11, 2011 at 1:16 PM, Kirill Yukhin <kirill.yuk...@gmail.com> wrote: > Hi Uros, > Thanks for patience reviewing my English :) and for finding a bug in souces. > > Updated patch is attached. It was bootstrapped successfully. > > updated ChangeLog entry: > > 2011-08-11 Kirill Yukhin <kirill.yuk...@intel.com> > > * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX2_SET): New. > (OPTION_MASK_ISA_AVX_UNSET): Update. > (OPTION_MASK_ISA_AVX2_UNSET): New. > (ix86_handle_option): Handle OPT_mavx2 case. > * config/i386/cpuid.h (bit_AVX2): New. > * config/i386/driver-i386.c (host_detect_local_cpu): Detect > AVX2 feature. > * config/i386/i386-c.c (ix86_target_macros_internal): > Conditionally define __AVX2__. > * config/i386/i386.c (ix86_option_override_internal): Define > PTA_AVX2. Define "core-avx2" processor alias. Handle avx2 > option. > (ix86_valid_target_attribute_inner_p): Handle avx2 option. > * config/i386/i386.h (TARGET_AVX2): New. > * config/i386/i386.opt (mavx2): New. > * doc/invoke.texi: Document -mavx2. > > > Seems, from now on we have to wait for int64 patch to be approved and > comitted to trunk.. > > -- > Thanks, K > > On Wed, Aug 10, 2011 at 11:41 PM, Uros Bizjak <ubiz...@gmail.com> wrote: >> On Wed, Aug 10, 2011 at 9:39 PM, Uros Bizjak <ubiz...@gmail.com> wrote: >> >>> diff --git a/gcc/common/config/i386/i386-common.c >>> b/gcc/common/config/i386/i386-common.c >>> index 1fd33bd..1e0ca5e 100644 >>> --- a/gcc/common/config/i386/i386-common.c >>> +++ b/gcc/common/config/i386/i386-common.c >>> @@ -52,6 +52,8 @@ along with GCC; see the file COPYING3. If not see >>> (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET) >>> #define OPTION_MASK_ISA_FMA_SET \ >>> (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET) >>> +#define OPTION_MASK_ISA_AVX2_SET \ >>> + (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX_SET) >>> >>> /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same >>> as -msse4.2. */ >>> @@ -114,8 +116,10 @@ along with GCC; see the file COPYING3. If not see >>> (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET ) >>> #define OPTION_MASK_ISA_AVX_UNSET \ >>> (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \ >>> - | OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET) >>> + | OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET \ >>> + | OPTION_MASK_ISA_AVX) >>> >>> OPTION_MASK_ISA_AVX2 >> >> Hrm, OPTION_MASK_ISA_AVX2_UNSET. >> >> Uros. >> >
