Hi! vpshufb is AVX512BW & AVX512VL insn, so we shouldn't allow it for AVX512VL only.
Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? 2016-05-13 Jakub Jelinek <ja...@redhat.com> * config/i386/sse.md (<ssse3_avx2>_pshufb<mode>3<mask_name>): Use constraint x instead of v in second alternative, add avx512bw alternative. * gcc.target/i386/avx512vl-vpshufb-3.c: New test. * gcc.target/i386/avx512bw-vpshufb-3.c: New test. --- gcc/config/i386/sse.md.jj 2016-05-13 15:18:24.791195754 +0200 +++ gcc/config/i386/sse.md 2016-05-13 15:47:50.978978445 +0200 @@ -14206,21 +14206,22 @@ (define_insn "*ssse3_pmulhrswv4hi3" (set_attr "mode" "DI")]) (define_insn "<ssse3_avx2>_pshufb<mode>3<mask_name>" - [(set (match_operand:VI1_AVX512 0 "register_operand" "=x,v") + [(set (match_operand:VI1_AVX512 0 "register_operand" "=x,x,v") (unspec:VI1_AVX512 - [(match_operand:VI1_AVX512 1 "register_operand" "0,v") - (match_operand:VI1_AVX512 2 "vector_operand" "xBm,vm")] + [(match_operand:VI1_AVX512 1 "register_operand" "0,x,v") + (match_operand:VI1_AVX512 2 "vector_operand" "xBm,xm,vm")] UNSPEC_PSHUFB))] "TARGET_SSSE3 && <mask_mode512bit_condition> && <mask_avx512bw_condition>" "@ pshufb\t{%2, %0|%0, %2} + vpshufb\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2} vpshufb\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" - [(set_attr "isa" "noavx,avx") + [(set_attr "isa" "noavx,avx,avx512bw") (set_attr "type" "sselog1") - (set_attr "prefix_data16" "1,*") + (set_attr "prefix_data16" "1,*,*") (set_attr "prefix_extra" "1") - (set_attr "prefix" "orig,maybe_evex") - (set_attr "btver2_decode" "vector,vector") + (set_attr "prefix" "orig,maybe_evex,evex") + (set_attr "btver2_decode" "vector") (set_attr "mode" "<sseinsnmode>")]) (define_insn "ssse3_pshufbv8qi3" --- gcc/testsuite/gcc.target/i386/avx512vl-vpshufb-3.c.jj 2016-05-13 15:42:41.261220799 +0200 +++ gcc/testsuite/gcc.target/i386/avx512vl-vpshufb-3.c 2016-05-13 15:43:09.052841972 +0200 @@ -0,0 +1,30 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mavx512vl -mno-avx512bw" } */ + +#include <x86intrin.h> + +void +f1 (__m128i x, __m128i y) +{ + register __m128i a __asm ("xmm16"), b __asm ("xmm17"); + a = x; + b = y; + asm volatile ("" : "+v" (a), "+v" (b)); + a = _mm_shuffle_epi8 (a, b); + asm volatile ("" : "+v" (a)); +} + +/* { dg-final { scan-assembler-not "vpshufb\[^\n\r]*xmm1\[67]" } } */ + +void +f2 (__m256i x, __m256i y) +{ + register __m256i a __asm ("xmm16"), b __asm ("xmm17"); + a = x; + b = y; + asm volatile ("" : "+v" (a), "+v" (b)); + a = _mm256_shuffle_epi8 (a, b); + asm volatile ("" : "+v" (a)); +} + +/* { dg-final { scan-assembler-not "vpshufb\[^\n\r]*ymm1\[67]" } } */ --- gcc/testsuite/gcc.target/i386/avx512bw-vpshufb-3.c.jj 2016-05-13 15:42:23.788458969 +0200 +++ gcc/testsuite/gcc.target/i386/avx512bw-vpshufb-3.c 2016-05-13 15:41:15.000000000 +0200 @@ -0,0 +1,30 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mavx512vl -mavx512bw" } */ + +#include <x86intrin.h> + +void +f1 (__m128i x, __m128i y) +{ + register __m128i a __asm ("xmm16"), b __asm ("xmm17"); + a = x; + b = y; + asm volatile ("" : "+v" (a), "+v" (b)); + a = _mm_shuffle_epi8 (a, b); + asm volatile ("" : "+v" (a)); +} + +/* { dg-final { scan-assembler "vpshufb\[^\n\r]*xmm1\[67]\[^\n\r]*xmm1\[67]\[^\n\r]*xmm1\[67]" } } */ + +void +f2 (__m256i x, __m256i y) +{ + register __m256i a __asm ("xmm16"), b __asm ("xmm17"); + a = x; + b = y; + asm volatile ("" : "+v" (a), "+v" (b)); + a = _mm256_shuffle_epi8 (a, b); + asm volatile ("" : "+v" (a)); +} + +/* { dg-final { scan-assembler "vpshufb\[^\n\r]*ymm1\[67]\[^\n\r]*ymm1\[67]\[^\n\r]*ymm1\[67]" } } */ Jakub