On Tue, May 17, 2016 at 06:45:49PM -0400, Michael Meissner wrote:
> As I mentioned in the last message, my previous patch had some problems that
> showed up on big endian systems, using RELOAD (one of the tests that failed
> was
> the vshuf-v32qi.c test in the testsuite). Little endian and IRA did compiled
> the test fine. This patch fixes the problem. I went over the alternatives in
> the vsx_mov<mode>_{32bit,64bit} patterns, and I removed the '*' constraints,
> and checked all of the other constraints.
So those * is the only change?
> The patches bootstrap and pass regression tests on both little endian power8
> and big endian power7 systems. Are these patches ok to install in the trunk?
This patch is okay for trunk.
> After a burn-in period, will they be ok to back port to the GCC 6.2 branch?
Yes. Please make sure you test it there as well (BE/LE, p7/p8).
A few nits still:
> +(define_predicate "xxspltib_constant_split"
> + (match_code "const_vector,vec_duplicate,const_int")
> +{
> + int value = 256;
> + int num_insns = -1;
Still has a tab character.
> +(define_predicate "xxspltib_constant_nosplit"
> + (match_code "const_vector,vec_duplicate,const_int")
> +{
> + int value = 256;
> + int num_insns = -1;
And here.
> @@ -1024,6 +1068,10 @@ (define_predicate "splat_input_operand"
> mode = V2DFmode;
> else if (mode == DImode)
> mode = V2DImode;
> + else if (mode == SImode && TARGET_P9_VECTOR)
> + mode = V4SImode;
> + else if (mode == SFmode && TARGET_P9_VECTOR)
> + mode = V4SFmode;
Trailing tabs (twice).
> +;; VSX store VSX load VSX move VSX->GPR GPR->VSX LQ (GPR)
> +;; STQ (GPR) GPR load GPR store GPR move XXSPLTIB
> VSPLTISW
> +;; VSX 0/-1 GPR 0/-1 VMX const GPR const LVX (VMX) STVX
> (VMX)
> +(define_insn "*vsx_mov<mode>_64bit"
> + [(set (match_operand:VSX_M 0 "nonimmediate_operand"
> + "=ZwO, <VSa>, <VSa>, r, we, ?wQ,
> + ?&r, ??r, ??Y, ??r, wo, v,
> + ?<VSa>, *r, v, ??r, wZ, v")
> +
> + (match_operand:VSX_M 1 "input_operand"
> + "<VSa>, ZwO, <VSa>, we, r, r,
> + wQ, Y, r, r, wE, jwM,
> + ?jwM, jwM, W, W, v, wZ"))]
> +
> + "TARGET_POWERPC64 && VECTOR_MEM_VSX_P (<MODE>mode)
> + && (register_operand (operands[0], <MODE>mode)
> + || register_operand (operands[1], <MODE>mode))"
> +{
> + return rs6000_output_move_128bit (operands);
> +}
> + [(set_attr "type"
> + "vecstore, vecload, vecsimple, mffgpr, mftgpr, load,
> + store, load, store, *, vecsimple,
> vecsimple,
> + vecsimple, *, *, *, vecstore, vecload")
> +
> + (set_attr "length"
> + "4, 4, 4, 8, 4, 8,
> + 8, 8, 8, 8, 4, 4,
> + 4, 8, 20, 20, 4, 4")])
Some of these lines are indented with spaces instead of tabs, please fix.
Looks great otherwise, thanks!
> +;; V4SI splat (ISA 3.0)
> +;; When SI's are allowed in VSX registers, add XXSPLTW support
> +(define_expand "vsx_splat_<mode>"
> + [(set (match_operand:VSX_W 0 "vsx_register_operand" "")
> + (vec_duplicate:VSX_W
> + (match_operand:<VS_scalar> 1 "splat_input_operand" "")))]
You can leave off the default arg "" nowadays. I know we're not consistent
in that.
Segher
