On Thu, May 19, 2016 at 10:53:41AM -0400, Michael Meissner wrote: > GCC 6.1 added support for the XXPERM instruction for the PowerPC ISA 3.0. The > XXPERM instruction is essentially a 4 operand instruction, with only 3 > operands > in the instruction (the target register overlaps with the first input > register). The Power9 hardware has fusion support where if the instruction > that precedes the XXPERM is a XXLOR move instruction to set the first input > argument, it is fused with the XXPERM. I added code to support this fusion. > > Unfortunately, in running the testsuite on the power9 simulator, we discovered > that the test gcc.c-torture/execute/pr56866.c would fail because the fusion > alternatives confused the register allocator and/or the passes after the > register allocator. This patch removes the explicit fusion support from > XXPERM.
Okay. Please keep the PR open until that problem is fixed. It also shouldn't be "target" category, if the problem is RA. > In addition, ISA 3.0 added XXPERMR and VPERMR instructions for little endian > support where the permute vector reverses the bytes. This patch adds support > for XXPERMR/VPERMR. Please send that as a separate patch, it has nothing to do with the PR. > + x = gen_rtx_UNSPEC (mode, > + gen_rtvec (3, target, reg, Trailing space. > + if (TARGET_P9_VECTOR) > + { > + unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op0, op1, sel), And another. > + The VNAND is preferred for future fusion opportunities. */ > + notx = gen_rtx_NOT (V16QImode, sel); > + iorx = (TARGET_P8_VECTOR > + ? gen_rtx_IOR (V16QImode, notx, notx) > + : gen_rtx_AND (V16QImode, notx, notx)); > + emit_insn (gen_rtx_SET (norreg, iorx)); > + Some more. > +/* { dg-final { scan-assembler "vpermr\|xxpermr" } } */ Tab in the middle of the line. Segher