On Mon, 2016-06-06 at 17:27 +0000, Joseph Myers wrote: > This patch is missing the invoke.texi changes to document all the new > CPU > names.
Hi, correct, please consider adding the following patch to fix this. Regards. --- diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index ce162a0..ac7f8a8 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -23261,6 +23261,54 @@ VIA C3-2 (Nehemiah/C5XL) CPU with MMX and SSE instruction set support. (No scheduling is implemented for this chip.) +@item c7 +VIA C7 (Esther) CPU with MMX, SSE, SSE2 and SSE3 instruction set support. +(No scheduling is implemented for this chip.) + +@item samuel-2 +VIA Eden Samuel 2 CPU with MMX and 3DNow!@: instruction set support. +(No scheduling is implemented for this chip.) + +@item nehemiah +VIA Eden Nehemiah CPU with MMX and SSE instruction set support. +(No scheduling is implemented for this chip.) + +@item esther +VIA Eden Esther CPU with MMX, SSE, SSE2 and SSE3 instruction set support. +(No scheduling is implemented for this chip.) + +@item eden-x2 +VIA Eden X2 CPU with x86-64, MMX, SSE, SSE2 and SSE3 instruction set support. +(No scheduling is implemented for this chip.) + +@item eden-x4 +VIA Eden X4 CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and AVX2 instruction set support. +(No scheduling is implemented for this chip.) + +@item nano +Generic VIA Nano CPU with x86-64, MMX, SSE, SSE2, SSE3 and SSSE3 instruction set support. +(No scheduling is implemented for this chip.) + +@item nano-1000 +VIA Nano 1xxx CPU with x86-64, MMX, SSE, SSE2, SSE3 and SSSE3 instruction set support. +(No scheduling is implemented for this chip.) + +@item nano-2000 +VIA Nano 2xxx CPU with x86-64, MMX, SSE, SSE2, SSE3 and SSSE3 instruction set support. +(No scheduling is implemented for this chip.) + +@item nano-3000 +VIA Nano 3xxx CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 instruction set support. +(No scheduling is implemented for this chip.) + +@item nano-x2 +VIA Nano Dual Core CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 instruction set support. +(No scheduling is implemented for this chip.) + +@item nano-x4 +VIA Nano Quad Core CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 instruction set support. +(No scheduling is implemented for this chip.) + @item geode AMD Geode embedded processor with MMX and 3DNow!@: instruction set support. @end table