On Wed, Jul 13, 2016 at 07:43:13PM +0200, Bernd Schmidt wrote:
> On 07/13/2016 05:29 PM, Dominik Vogt wrote:
>
> >Unfortunately this patch (or whatever got actually committed) has
> >broken the gcc.target/s390/pr679443.c test case, which is a bit
> >fishy (see code snippet below). I assign most registers to global
> >variables and then use some complicated arithmetics with the goal
> >that the pointer stored in the first argument gets saved on the
> >stack and reloaded to a different register. Before this patch the
> >test case just needed three registers to do its work (r2, r3, r4).
> >With the patch it currently causes an error in the reload pass
> >
> > error: unable to find a register to spill
>
> Might be useful to see the dump_reload output.
Attached.
> >If a fourth register is available, the ICE goes away, but the
> >pointer remains in r2, rendering the test case useless.
>
> I don't think I quite understand what you're trying to do here,
Alias detection of the memory pointed to by the first register.
There was some hard to trigger bug where writing a bitfield in a
struct would also overwrite the unselected bits of the
corresponding word. See here:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67443
> but it does look dodgy.
It is. The problem is that I can't tell Gcc to move the address
to a different register directly, so I had to do some voodoo
to achieve that. The test case seemed to be the most robust
approach ...
> Whatever this is testing would probably be
> better as a part of a unit test.o
I've spent a lot of time to port the test to Power but was unable
to reproduce the effect.
Ciao
Dominik ^_^ ^_^
--
Dominik Vogt
IBM Germany
;; Function foo (foo, funcdef_no=0, decl_uid=2002, cgraph_uid=0, symbol_order=9)
********** Local #1: **********
Spilling non-eliminable hard regs: 15 35
New elimination table:
Can eliminate 34 to 15 (offset=160, prev_offset=0)
Can eliminate 34 to 11 (offset=160, prev_offset=0)
Can eliminate 32 to 15 (offset=160, prev_offset=0)
Can eliminate 32 to 11 (offset=160, prev_offset=0)
Can't eliminate 35 to 15 (offset=0, prev_offset=0)
Can't eliminate 35 to 11 (offset=0, prev_offset=0)
Can eliminate 13 to 13 (offset=0, prev_offset=0)
alt=0: Bad operand -- refuse
alt=1: Bad operand -- refuse
alt=2: Bad operand -- refuse
alt=3: Bad operand -- refuse
alt=4: Bad operand -- refuse
alt=12,overall=0,losers=0,rld_nregs=0
Choosing alt 12 in insn 4: (0) d (1) d {*movdi_64}
0 Non input pseudo reload: reject++
1 Matching alt: reject+=2
2 Non-pseudo reload: reject+=2
2 Non input pseudo reload: reject++
alt=0,overall=24,losers=3,rld_nregs=4
0 Non input pseudo reload: reject++
1 Matching alt: reject+=2
2 Non input pseudo reload: reject++
alt=1,overall=22,losers=3,rld_nregs=3
Choosing alt 1 in insn 9: (0) d (1) 0 (2) T {divmodtidi3}
Creating newreg=78 from oldreg=71, assigning class GENERAL_REGS to r78
9:
r78:TI=zero_extend(r78:TI#8%[`*.LC0'])<<0x40|zero_extend(r78:TI#8/[`*.LC0'])
Inserting insn reload before:
23: clobber r78:TI
24: r78:TI#8=r67:DI
Inserting insn reload after:
25: r71:TI=r78:TI
0 Non input pseudo reload: reject++
alt=0,overall=613,losers=2,rld_nregs=2
0 Non pseudo reload: reject++
1 Non pseudo reload: reject++
alt=1,overall=2,losers=0,rld_nregs=0
Choosing alt 1 in insn 25: (0) S (1) d {movti}
0 Non pseudo reload: reject++
alt=0: Bad operand -- refuse
0 Non pseudo reload: reject++
alt=1: Bad operand -- refuse
0 Non pseudo reload: reject++
alt=2: Bad operand -- refuse
0 Non pseudo reload: reject++
alt=3: Bad operand -- refuse
0 Non pseudo reload: reject++
alt=4: Bad operand -- refuse
0 Non pseudo reload: reject++
alt=12,overall=1,losers=0,rld_nregs=0
Choosing alt 12 in insn 24: (0) d (1) d {*movdi_64}
alt=0: Bad operand -- refuse
alt=1: Bad operand -- refuse
alt=2: Bad operand -- refuse
alt=3: Bad operand -- refuse
alt=4: Bad operand -- refuse
alt=12,overall=0,losers=0,rld_nregs=0
Choosing alt 12 in insn 2: (0) d (1) d {*movdi_64}
alt=0,overall=6,losers=1,rld_nregs=1
alt=2: Bad operand -- refuse
2 Spill pseudo into memory: reject+=3
alt=6,overall=15,losers=2 -- refuse
alt=0,overall=6,losers=1,rld_nregs=1
alt=2: Bad operand -- refuse
2 Non pseudo reload: reject++
alt=6,overall=1,losers=0,rld_nregs=0
Commutative operand exchange in insn 12
Choosing alt 6 in insn 12: (0) d (1) 0 (2) R {*addsi3}
alt=0: Bad operand -- refuse
1 Spill pseudo into memory: reject+=3
alt=1: Bad operand -- refuse
alt=2,overall=0,losers=0,rld_nregs=0
1 Non-pseudo reload: reject+=2
1 Non input pseudo reload: reject++
alt=0,overall=15,losers=2 -- refuse
1 Non input pseudo reload: reject++
alt=1,overall=7,losers=1 -- refuse
1 Matching alt: reject+=2
1 Non-pseudo reload: reject+=2
1 Non input pseudo reload: reject++
alt=2,overall=17,losers=2 -- refuse
1 Matching alt: reject+=2
1 Non-pseudo reload: reject+=2
1 Non input pseudo reload: reject++
alt=3,overall=17,losers=2 -- refuse
1 Matching alt: reject+=2
1 Non-pseudo reload: reject+=2
1 Non input pseudo reload: reject++
alt=4,overall=17,losers=2 -- refuse
1 Matching alt: reject+=2
1 Non-pseudo reload: reject+=2
1 Non input pseudo reload: reject++
alt=5,overall=17,losers=2 -- refuse
1 Matching alt: reject+=2
1 Non-pseudo reload: reject+=2
1 Non input pseudo reload: reject++
alt=7,overall=17,losers=2 -- refuse
0 Spill pseudo into memory: reject+=3
0 Non input pseudo reload: reject++
alt=10,overall=10,losers=1 -- refuse
0 Spill pseudo into memory: reject+=3
0 Non input pseudo reload: reject++
alt=11,overall=10,losers=1 -- refuse
Choosing alt 2 in insn 14: (0) d (1) 0 (2) N0HSF {*andsi3_zarch}
0 Non-pseudo reload: reject+=2
0 Non input pseudo reload: reject++
alt=0,overall=609,losers=1,rld_nregs=1
0 Non-pseudo reload: reject+=2
0 Non input pseudo reload: reject++
alt=1: Bad operand -- refuse
0 Non-pseudo reload: reject+=2
0 Non input pseudo reload: reject++
1 Non-pseudo reload: reject+=2
1 Spill pseudo into memory: reject+=3
alt=2,overall=20,losers=2,rld_nregs=1
alt=4,overall=0,losers=0,rld_nregs=0
Choosing alt 4 in insn 8: (0) R (1) d {*movqi}
1 Non-pseudo reload: reject+=2
1 Non input pseudo reload: reject++
alt=0: Bad operand -- refuse
alt=1: Bad operand -- refuse
1 Matching alt: reject+=2
1 Non-pseudo reload: reject+=2
1 Non input pseudo reload: reject++
alt=2: Bad operand -- refuse
1 Matching alt: reject+=2
1 Non-pseudo reload: reject+=2
1 Non input pseudo reload: reject++
alt=3: Bad operand -- refuse
1 Matching alt: reject+=2
1 Non-pseudo reload: reject+=2
1 Non input pseudo reload: reject++
alt=4: Bad operand -- refuse
1 Matching alt: reject+=2
1 Non-pseudo reload: reject+=2
1 Non input pseudo reload: reject++
2 Non-pseudo reload: reject+=2
2 Non input pseudo reload: reject++
alt=5,overall=26,losers=3,rld_nregs=2
1 Matching alt: reject+=2
1 Non-pseudo reload: reject+=2
1 Non input pseudo reload: reject++
2 Non input pseudo reload: reject++
alt=7,overall=18,losers=2,rld_nregs=1
0 Spill pseudo into memory: reject+=3
0 Non input pseudo reload: reject++
alt=10: Bad operand -- refuse
0 Spill pseudo into memory: reject+=3
0 Non input pseudo reload: reject++
alt=11: Bad operand -- refuse
1 Non-pseudo reload: reject+=2
1 Non input pseudo reload: reject++
alt=0: Bad operand -- refuse
1 Non input pseudo reload: reject++
alt=1: Bad operand -- refuse
1 Matching alt: reject+=2
1 Non-pseudo reload: reject+=2
1 Non input pseudo reload: reject++
alt=2: Bad operand -- refuse
1 Matching alt: reject+=2
1 Non-pseudo reload: reject+=2
1 Non input pseudo reload: reject++
alt=3: Bad operand -- refuse
1 Matching alt: reject+=2
1 Non-pseudo reload: reject+=2
1 Non input pseudo reload: reject++
alt=4: Bad operand -- refuse
1 Matching alt: reject+=2
1 Non-pseudo reload: reject+=2
1 Non input pseudo reload: reject++
2 Non-pseudo reload: reject+=2
2 Non input pseudo reload: reject++
alt=5,overall=26,losers=3 -- refuse
1 Matching alt: reject+=2
1 Non-pseudo reload: reject+=2
1 Non input pseudo reload: reject++
alt=7,overall=17,losers=2,rld_nregs=1
0 Spill pseudo into memory: reject+=3
0 Non input pseudo reload: reject++
alt=10: Bad operand -- refuse
0 Spill pseudo into memory: reject+=3
0 Non input pseudo reload: reject++
alt=11: Bad operand -- refuse
Commutative operand exchange in insn 16
Choosing alt 7 in insn 16: (0) d (1) 0 (2) R {*andsi3_zarch}
Creating newreg=79 from oldreg=76, assigning class GENERAL_REGS to r79
16: {r79:SI=r79:SI&[r65:DI];clobber %cc:CC;}
REG_UNUSED %cc:CC
Inserting insn reload before:
26: r79:SI=[`*.LC1']
Inserting insn reload after:
27: r76:SI=r79:SI
alt=0: Bad operand -- refuse
alt=1: Bad operand -- refuse
alt=2: Bad operand -- refuse
1 Non pseudo reload: reject++
alt=6,overall=1,losers=0,rld_nregs=0
Choosing alt 6 in insn 27: (0) d (1) d {*movsi_zarch}
0 Non pseudo reload: reject++
alt=0: Bad operand -- refuse
0 Non pseudo reload: reject++
alt=1: Bad operand -- refuse
0 Non pseudo reload: reject++
alt=2: Bad operand -- refuse
0 Non pseudo reload: reject++
1 Non-pseudo reload: reject+=2
1 Non input pseudo reload: reject++
alt=6,overall=610,losers=1,rld_nregs=1
0 Non pseudo reload: reject++
alt=7,overall=1,losers=0,rld_nregs=0
Choosing alt 7 in insn 26: (0) d (1) R {*movsi_zarch}
alt=0: Bad operand -- refuse
alt=1: Bad operand -- refuse
alt=2: Bad operand -- refuse
alt=3,overall=6,losers=1,rld_nregs=1
2 Spill pseudo into memory: reject+=3
alt=5,overall=15,losers=2 -- refuse
0 Spill pseudo into memory: reject+=3
0 Non input pseudo reload: reject++
alt=7,overall=10,losers=1 -- refuse
0 Spill pseudo into memory: reject+=3
0 Non input pseudo reload: reject++
alt=8,overall=10,losers=1 -- refuse
alt=0: Bad operand -- refuse
alt=1: Bad operand -- refuse
alt=2: Bad operand -- refuse
alt=3,overall=0,losers=0,rld_nregs=0
Commutative operand exchange in insn 17
Choosing alt 3 in insn 17: (0) d (1) 0 (2) d {*iorsi3_zarch}
0 Non-pseudo reload: reject+=2
0 Non input pseudo reload: reject++
alt=0: Bad operand -- refuse
0 Non-pseudo reload: reject+=2
0 Non input pseudo reload: reject++
alt=1: Bad operand -- refuse
0 Non-pseudo reload: reject+=2
0 Non input pseudo reload: reject++
alt=2: Bad operand -- refuse
0 Non-pseudo reload: reject+=2
0 Non input pseudo reload: reject++
alt=6,overall=609,losers=1,rld_nregs=1
0 Non-pseudo reload: reject+=2
0 Non input pseudo reload: reject++
1 Spill pseudo into memory: reject+=3
alt=7,overall=18,losers=2,rld_nregs=1
alt=9,overall=0,losers=0,rld_nregs=0
Choosing alt 9 in insn 18: (0) R (1) d {*movsi_zarch}
Elimination 13 to 13 is not possible anymore
13 is not eliminable at all
Spilling non-eliminable hard regs: 13 15 35
********** Pseudo live ranges #1: **********
BB 2
Insn 18: point = 0
Insn 17: point = 1
Insn 27: point = 3
Hard reg 3 is preferable by r79 with profit 1000
Insn 16: point = 5
Insn 26: point = 5
Insn 8: point = 6
Insn 14: point = 6
Insn 12: point = 8
Insn 2: point = 10
Insn 25: point = 11
Insn 9: point = 13
Insn 24: point = 15
Insn 23: point = 15
Insn 4: point = 16
r65: [0..10]
r67: [9..16]
r71: [9..11]
r72: [7..8]
r74: [2..6]
r76: [2..3]
r77: [0..1]
r78: [12..15]
r79: [4..5]
Compressing live ranges: from 17 to 12 - 70%
Ranges after the compression:
r65: [0..9]
r67: [8..11]
r71: [8..9]
r72: [6..7]
r74: [2..5]
r76: [2..3]
r77: [0..1]
r78: [10..11]
r79: [4..5]
********** Inheritance #1: **********
EBB 2
<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
Creating newreg=80 from oldreg=71, assigning class GENERAL_REGS to
inheritance r80
Original reg change 71->80 (bb2):
25: r80:TI=r78:TI
REG_DEAD r78:TI
Add original<-inheritance after:
28: r71:TI=r80:TI
Inheritance reuse change 71->80 (bb2):
12: {r72:SI=r67:DI#4+r80:TI#4;clobber %cc:CC;}
REG_DEAD r80:TI
REG_DEAD r67:DI
REG_UNUSED %cc:CC
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
Removing dead insn:
28: r71:TI=r80:TI
deleting insn with uid = 28.
********** Pseudo live ranges #2: **********
BB 2
Insn 18: point = 0
Insn 17: point = 1
Insn 27: point = 3
Hard reg 3 is preferable by r79 with profit 1000
Insn 16: point = 5
Insn 26: point = 5
Insn 8: point = 6
Insn 14: point = 6
Insn 12: point = 8
Insn 2: point = 10
Insn 25: point = 11
Creating copy r78->r80@1000
Insn 9: point = 13
Insn 24: point = 15
Insn 23: point = 15
Insn 4: point = 16
r65: [0..10]
r67: [9..16]
r72: [7..8]
r74: [2..6]
r76: [2..3]
r77: [0..1]
r78: [12..15]
r79: [4..5]
r80: [9..11]
Compressing live ranges: from 17 to 12 - 70%
Ranges after the compression:
r65: [0..9]
r67: [8..11]
r72: [6..7]
r74: [2..5]
r76: [2..3]
r77: [0..1]
r78: [10..11]
r79: [4..5]
r80: [8..9]
********** Assignment #1: **********
Assigning to 78 (cl=GENERAL_REGS, orig=71, freq=5000, tfirst=78,
tfreq=5000)...
Trying 1:
Trying 2:
Trying 3: spill 67(freq=3000)
Trying 4: spill 67(freq=3000)
Trying 5:
Trying 0:
Trying 11:
Trying 10:
Trying 9:
Trying 8:
Trying 7:
Trying 6:
Trying 14:
Trying 13:
Assigning to 80 (cl=GENERAL_REGS, orig=71, freq=2000, tfirst=78,
tfreq=5000)...
Assigning to 79 (cl=GENERAL_REGS, orig=76, freq=3000, tfirst=79,
tfreq=3000)...
Assign 3 to reload r79 (freq=3000)
2nd iter for reload pseudo assignments:
Reload r78 assignment failure
Spill r67(hr=4, freq=3000)
Assigning to 78 (cl=GENERAL_REGS, orig=71, freq=5000, tfirst=78,
tfreq=5000)...
Trying 1:
Trying 2:
Trying 3:
Trying 4:
Trying 5:
Trying 0:
Trying 11:
Trying 10:
Trying 9:
Trying 8:
Trying 7:
Trying 6:
Trying 14:
Trying 13:
Assign 1 to reload r78 (freq=5000)
Hard reg 1 is preferable by r80 with profit 1000
