Hi gcc-patches group,
Please find the patch for adding the basic scheduler for vulcan
in the aarch64 port.
Tested the patch with compiling cross aarch64-linux-gcc,
bootstrapped native aarch64-unknown-linux-gnu and
run gcc regression.
Kindly review and merge the patch to trunk, if the patch is okay.
There are few TODO in this patch which we have planned to
submit in the next submission e.g. crc and crypto
instructions, further improving integer & fp load/store
based on addressing mode of the address.
Thanks.
gcc/ChangeLog:
Virendra Pathak <virendra.pat...@broadcom.com>
Julian Brown <jul...@codesourcery.com>
* config/aarch64/aarch64-cores.def: Change the scheduler
to vulcan.
* config/aarch64/aarch64.md: Include vulcan.md.
* config/aarch64/vulcan.md: New file.
with regards,
Virendra Pathak
From 3114daf5a5b4e7f1bbc57f0bf930823615c7d6aa Mon Sep 17 00:00:00 2001
From: Virendra Pathak <virendra.pat...@broadcom.com>
Date: Thu, 14 Jul 2016 23:07:10 -0700
Subject: [PATCH] AArch64: Add scheduler for vulcan.
---
gcc/config/aarch64/aarch64-cores.def | 2 +-
gcc/config/aarch64/aarch64.md | 1 +
gcc/config/aarch64/vulcan.md | 490 +++++++++++++++++++++++++++++++++++
3 files changed, 492 insertions(+), 1 deletion(-)
create mode 100644 gcc/config/aarch64/vulcan.md
diff --git a/gcc/config/aarch64/aarch64-cores.def
b/gcc/config/aarch64/aarch64-cores.def
index d9da257..b3bfece 100644
--- a/gcc/config/aarch64/aarch64-cores.def
+++ b/gcc/config/aarch64/aarch64-cores.def
@@ -52,7 +52,7 @@ AARCH64_CORE("xgene1", xgene1, xgene1, 8A,
AARCH64_FL_FOR_ARCH8, xge
/* V8.1 Architecture Processors. */
-AARCH64_CORE("vulcan", vulcan, cortexa57, 8_1A, AARCH64_FL_FOR_ARCH8_1 |
AARCH64_FL_CRYPTO, vulcan, "0x42", "0x516")
+AARCH64_CORE("vulcan", vulcan, vulcan, 8_1A, AARCH64_FL_FOR_ARCH8_1 |
AARCH64_FL_CRYPTO, vulcan, "0x42", "0x516")
/* V8 big.LITTLE implementations. */
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index bcb7db0..5d754b1 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -219,6 +219,7 @@
(include "../arm/exynos-m1.md")
(include "thunderx.md")
(include "../arm/xgene1.md")
+(include "vulcan.md")
;; -------------------------------------------------------------------
;; Jumps and other miscellaneous insns
diff --git a/gcc/config/aarch64/vulcan.md b/gcc/config/aarch64/vulcan.md
new file mode 100644
index 0000000..d54044f
--- /dev/null
+++ b/gcc/config/aarch64/vulcan.md
@@ -0,0 +1,490 @@
+;; Broadcom Vulcan pipeline description
+;; Copyright (C) 2016 Free Software Foundation, Inc.
+;;
+;; Contributed by Broadcom and Mentor Embedded.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
+
+(define_automaton "vulcan")
+
+(define_cpu_unit "vulcan_i0" "vulcan")
+(define_cpu_unit "vulcan_i1" "vulcan")
+(define_cpu_unit "vulcan_i2" "vulcan")
+(define_cpu_unit "vulcan_ls0" "vulcan")
+(define_cpu_unit "vulcan_ls1" "vulcan")
+(define_cpu_unit "vulcan_sd" "vulcan")
+
+; Pseudo-units for multiply pipeline.
+
+(define_cpu_unit "vulcan_i1m1" "vulcan")
+(define_cpu_unit "vulcan_i1m2" "vulcan")
+(define_cpu_unit "vulcan_i1m3" "vulcan")
+
+; Pseudo-units for load delay (assuming dcache hit).
+
+(define_cpu_unit "vulcan_ls0d1" "vulcan")
+(define_cpu_unit "vulcan_ls0d2" "vulcan")
+(define_cpu_unit "vulcan_ls0d3" "vulcan")
+
+(define_cpu_unit "vulcan_ls1d1" "vulcan")
+(define_cpu_unit "vulcan_ls1d2" "vulcan")
+(define_cpu_unit "vulcan_ls1d3" "vulcan")
+
+; Make some aliases for f0/f1.
+(define_reservation "vulcan_f0" "vulcan_i0")
+(define_reservation "vulcan_f1" "vulcan_i1")
+
+(define_reservation "vulcan_i012" "vulcan_i0|vulcan_i1|vulcan_i2")
+(define_reservation "vulcan_ls01" "vulcan_ls0|vulcan_ls1")
+(define_reservation "vulcan_f01" "vulcan_f0|vulcan_f1")
+
+(define_reservation "vulcan_ls_both" "vulcan_ls0+vulcan_ls1")
+
+; A load with delay in the ls0/ls1 pipes.
+(define_reservation "vulcan_l0delay" "vulcan_ls0,vulcan_ls0d1,vulcan_ls0d2,\
+ vulcan_ls0d3")
+(define_reservation "vulcan_l1delay" "vulcan_ls1,vulcan_ls1d1,vulcan_ls1d2,\
+ vulcan_ls1d3")
+(define_reservation "vulcan_l01delay" "vulcan_l0delay|vulcan_l1delay")
+
+;; Branch and call instructions.
+
+(define_insn_reservation "vulcan_branch" 1
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "call,branch"))
+ "vulcan_i2")
+
+;; Integer arithmetic/logic instructions.
+
+; Plain register moves are handled by renaming, and don't create any uops.
+
+(define_insn_reservation "vulcan_regmove" 0
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "mov_reg"))
+ "nothing")
+
+(define_insn_reservation "vulcan_alu_basic" 1
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "alu_imm,alu_sreg,alus_imm,alus_sreg,\
+ adc_reg,adc_imm,adcs_reg,adcs_imm,\
+ logic_reg,logic_imm,logics_reg,logics_imm,\
+ csel,adr,mov_imm,shift_reg,shift_imm,bfm,\
+ rbit,rev,extend"))
+ "vulcan_i012")
+
+(define_insn_reservation "vulcan_alu_shift" 2
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "alu_shift_imm,alu_ext,alu_shift_reg,\
+ alus_shift_imm,alus_ext,alus_shift_reg,\
+ logic_shift_imm,logics_shift_reg"))
+ "vulcan_i012,vulcan_i012")
+
+(define_insn_reservation "vulcan_div" 13
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "sdiv,udiv"))
+ "vulcan_i1*13")
+
+(define_insn_reservation "vulcan_madd" 5
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "mla,smlal,umlal"))
+ "vulcan_i1,vulcan_i1m1,vulcan_i1m2,vulcan_i1m3,vulcan_i012")
+
+; NOTE: smull, umull are used for "high part" multiplies too.
+(define_insn_reservation "vulcan_mul" 4
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "mul,smull,umull"))
+ "vulcan_i1,vulcan_i1m1,vulcan_i1m2,vulcan_i1m3")
+
+(define_insn_reservation "vulcan_countbits" 3
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "clz"))
+ "vulcan_i1")
+
+;; Integer loads and stores.
+
+(define_insn_reservation "vulcan_load_basic" 4
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "load1"))
+ "vulcan_ls01")
+
+(define_insn_reservation "vulcan_loadpair" 5
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "load2"))
+ "vulcan_i012,vulcan_ls01")
+
+(define_insn_reservation "vulcan_store_basic" 1
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "store1"))
+ "vulcan_ls01,vulcan_sd")
+
+(define_insn_reservation "vulcan_storepair_basic" 1
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "store2"))
+ "vulcan_ls01,vulcan_sd")
+
+;; FP data processing instructions.
+
+(define_insn_reservation "vulcan_fp_simple" 5
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "ffariths,ffarithd,f_minmaxs,f_minmaxd"))
+ "vulcan_f01")
+
+(define_insn_reservation "vulcan_fp_addsub" 6
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "fadds,faddd"))
+ "vulcan_f01")
+
+(define_insn_reservation "vulcan_fp_cmp" 5
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "fcmps,fcmpd"))
+ "vulcan_f01")
+
+(define_insn_reservation "vulcan_fp_divsqrt_s" 16
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "fdivs,fsqrts"))
+ "vulcan_f0*8|vulcan_f1*8")
+
+(define_insn_reservation "vulcan_fp_divsqrt_d" 23
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "fdivd,fsqrtd"))
+ "vulcan_f0*12|vulcan_f1*12")
+
+(define_insn_reservation "vulcan_fp_mul_mac" 6
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "fmuls,fmuld,fmacs,fmacd"))
+ "vulcan_f01")
+
+(define_insn_reservation "vulcan_frint" 7
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "f_rints,f_rintd"))
+ "vulcan_f01")
+
+(define_insn_reservation "vulcan_fcsel" 4
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "fcsel"))
+ "vulcan_f01")
+
+;; FP miscellaneous instructions.
+
+(define_insn_reservation "vulcan_fp_cvt" 7
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "f_cvtf2i,f_cvt,f_cvti2f"))
+ "vulcan_f01")
+
+(define_insn_reservation "vulcan_fp_mov" 4
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "fconsts,fconstd,fmov,f_mrc"))
+ "vulcan_f01")
+
+(define_insn_reservation "vulcan_fp_mov_to_gen" 5
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "f_mcr"))
+ "vulcan_f01")
+
+;; FP loads and stores.
+
+(define_insn_reservation "vulcan_fp_load_basic" 4
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "f_loads,f_loadd"))
+ "vulcan_ls01")
+
+(define_insn_reservation "vulcan_fp_loadpair_basic" 4
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "neon_load1_2reg"))
+ "vulcan_ls01*2")
+
+(define_insn_reservation "vulcan_fp_store_basic" 1
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "f_stores,f_stored"))
+ "vulcan_ls01,vulcan_sd")
+
+(define_insn_reservation "vulcan_fp_storepair_basic" 1
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "neon_store1_2reg"))
+ "vulcan_ls01,(vulcan_ls01+vulcan_sd),vulcan_sd")
+
+;; ASIMD integer instructions.
+
+(define_insn_reservation "vulcan_asimd_int" 7
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "neon_abd,neon_abd_q,\
+ neon_arith_acc,neon_arith_acc_q,\
+ neon_abs,neon_abs_q,\
+ neon_add,neon_add_q,\
+ neon_neg,neon_neg_q,\
+ neon_add_long,neon_add_widen,\
+ neon_add_halve,neon_add_halve_q,\
+ neon_sub_long,neon_sub_widen,\
+ neon_sub_halve,neon_sub_halve_q,\
+ neon_add_halve_narrow_q,neon_sub_halve_narrow_q,\
+ neon_qabs,neon_qabs_q,\
+ neon_qadd,neon_qadd_q,\
+ neon_qneg,neon_qneg_q,\
+ neon_qsub,neon_qsub_q,\
+ neon_minmax,neon_minmax_q,\
+ neon_reduc_minmax,neon_reduc_minmax_q,\
+ neon_mul_b,neon_mul_h,neon_mul_s,\
+ neon_mul_b_q,neon_mul_h_q,neon_mul_s_q,\
+ neon_sat_mul_b,neon_sat_mul_h,neon_sat_mul_s,\
+ neon_sat_mul_b_q,neon_sat_mul_h_q,neon_sat_mul_s_q,\
+ neon_mla_b,neon_mla_h,neon_mla_s,\
+ neon_mla_b_q,neon_mla_h_q,neon_mla_s_q,\
+ neon_mul_b_long,neon_mul_h_long,\
+ neon_mul_s_long,neon_mul_d_long,\
+ neon_sat_mul_b_long,neon_sat_mul_h_long,\
+ neon_sat_mul_s_long,\
+ neon_mla_b_long,neon_mla_h_long,neon_mla_s_long,\
+ neon_sat_mla_b_long,neon_sat_mla_h_long,\
+ neon_sat_mla_s_long,\
+ neon_shift_acc,neon_shift_acc_q,\
+ neon_shift_imm,neon_shift_imm_q,\
+ neon_shift_reg,neon_shift_reg_q,\
+ neon_shift_imm_long,neon_shift_imm_narrow_q,\
+ neon_sat_shift_imm,neon_sat_shift_imm_q,\
+ neon_sat_shift_reg,neon_sat_shift_reg_q,\
+ neon_sat_shift_imm_narrow_q"))
+ "vulcan_f01")
+
+(define_insn_reservation "vulcan_asimd_reduc_add" 5
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "neon_reduc_add,neon_reduc_add_q"))
+ "vulcan_f01")
+
+(define_insn_reservation "vulcan_asimd_cmp" 7
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "neon_compare,neon_compare_q,neon_compare_zero,\
+ neon_tst,neon_tst_q"))
+ "vulcan_f01")
+
+(define_insn_reservation "vulcan_asimd_logic" 5
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "neon_logic,neon_logic_q"))
+ "vulcan_f01")
+
+;; ASIMD floating-point instructions.
+
+(define_insn_reservation "vulcan_asimd_fp_simple" 5
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "neon_fp_abs_s,neon_fp_abs_d,\
+ neon_fp_abs_s_q,neon_fp_abs_d_q,\
+ neon_fp_compare_s,neon_fp_compare_d,\
+ neon_fp_compare_s_q,neon_fp_compare_d_q,\
+ neon_fp_minmax_s,neon_fp_minmax_d,\
+ neon_fp_minmax_s_q,neon_fp_minmax_d_q,\
+ neon_fp_reduc_minmax_s,neon_fp_reduc_minmax_d,\
+ neon_fp_reduc_minmax_s_q,neon_fp_reduc_minmax_d_q,\
+ neon_fp_neg_s,neon_fp_neg_d,\
+ neon_fp_neg_s_q,neon_fp_neg_d_q"))
+ "vulcan_f01")
+
+(define_insn_reservation "vulcan_asimd_fp_arith" 6
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "neon_fp_abd_s,neon_fp_abd_d,\
+ neon_fp_abd_s_q,neon_fp_abd_d_q,\
+ neon_fp_addsub_s,neon_fp_addsub_d,\
+ neon_fp_addsub_s_q,neon_fp_addsub_d_q,\
+ neon_fp_reduc_add_s,neon_fp_reduc_add_d,\
+ neon_fp_reduc_add_s_q,neon_fp_reduc_add_d_q,\
+ neon_fp_mul_s,neon_fp_mul_d,\
+ neon_fp_mul_s_q,neon_fp_mul_d_q,\
+ neon_fp_mla_s,neon_fp_mla_d,\
+ neon_fp_mla_s_q,neon_fp_mla_d_q"))
+ "vulcan_f01")
+
+(define_insn_reservation "vulcan_asimd_fp_conv" 7
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "neon_fp_cvt_widen_s,neon_fp_cvt_narrow_d_q,\
+ neon_fp_to_int_s,neon_fp_to_int_d,\
+ neon_fp_to_int_s_q,neon_fp_to_int_d_q,\
+ neon_fp_round_s,neon_fp_round_d,\
+ neon_fp_round_s_q,neon_fp_round_d_q"))
+ "vulcan_f01")
+
+(define_insn_reservation "vulcan_asimd_fp_div_s" 16
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "neon_fp_div_s,neon_fp_div_s_q"))
+ "vulcan_f01")
+
+(define_insn_reservation "vulcan_asimd_fp_div_d" 23
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "neon_fp_div_d,neon_fp_div_d_q"))
+ "vulcan_f01")
+
+;; ASIMD miscellaneous instructions.
+
+(define_insn_reservation "vulcan_asimd_misc" 5
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "neon_rbit,\
+ neon_bsl,neon_bsl_q,\
+ neon_cls,neon_cls_q,\
+ neon_cnt,neon_cnt_q,\
+ neon_from_gp,neon_from_gp_q,\
+ neon_dup,neon_dup_q,\
+ neon_ext,neon_ext_q,\
+ neon_ins,neon_ins_q,\
+ neon_move,neon_move_q,\
+ neon_fp_recpe_s,neon_fp_recpe_d,\
+ neon_fp_recpe_s_q,neon_fp_recpe_d_q,\
+ neon_fp_recpx_s,neon_fp_recpx_d,\
+ neon_fp_recpx_s_q,neon_fp_recpx_d_q,\
+ neon_rev,neon_rev_q,\
+ neon_dup,neon_dup_q,\
+ neon_permute,neon_permute_q"))
+ "vulcan_f01")
+
+(define_insn_reservation "vulcan_asimd_recip_step" 6
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "neon_fp_recps_s,neon_fp_recps_s_q,\
+ neon_fp_recps_d,neon_fp_recps_d_q"))
+ "vulcan_f01")
+
+(define_insn_reservation "vulcan_asimd_lut" 8
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "neon_tbl1,neon_tbl1_q,neon_tbl2_q"))
+ "vulcan_f01")
+
+(define_insn_reservation "vulcan_asimd_elt_to_gr" 6
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "neon_to_gp,neon_to_gp_q"))
+ "vulcan_f01")
+
+;; ASIMD load instructions.
+
+; NOTE: These reservations attempt to model latency and throughput correctly,
+; but the cycle timing of unit allocation is not necessarily accurate (because
+; insns are split into uops, and those may be issued out-of-order).
+
+(define_insn_reservation "vulcan_asimd_load1_1_mult" 4
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "neon_load1_1reg,neon_load1_1reg_q"))
+ "vulcan_ls01")
+
+(define_insn_reservation "vulcan_asimd_load1_2_mult" 4
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "neon_load1_2reg,neon_load1_2reg_q"))
+ "vulcan_ls_both")
+
+(define_insn_reservation "vulcan_asimd_load1_3_mult" 5
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "neon_load1_3reg,neon_load1_3reg_q"))
+ "(vulcan_ls_both,vulcan_ls01)|(vulcan_ls01,vulcan_ls_both)")
+
+(define_insn_reservation "vulcan_asimd_load1_4_mult" 6
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "neon_load1_4reg,neon_load1_4reg_q"))
+ "vulcan_ls_both*2")
+
+(define_insn_reservation "vulcan_asimd_load1_onelane" 5
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "neon_load1_one_lane,neon_load1_one_lane_q"))
+ "vulcan_l01delay,vulcan_f01")
+
+(define_insn_reservation "vulcan_asimd_load1_all" 5
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "neon_load1_all_lanes,neon_load1_all_lanes_q"))
+ "vulcan_l01delay,vulcan_f01")
+
+(define_insn_reservation "vulcan_asimd_load2" 5
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "neon_load2_2reg,neon_load2_2reg_q,\
+ neon_load2_one_lane,neon_load2_one_lane_q,\
+ neon_load2_all_lanes,neon_load2_all_lanes_q"))
+ "(vulcan_l0delay,vulcan_f01)|(vulcan_l1delay,vulcan_f01)")
+
+(define_insn_reservation "vulcan_asimd_load3_mult" 8
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "neon_load3_3reg,neon_load3_3reg_q"))
+ "vulcan_ls_both*3,(vulcan_ls0d1+vulcan_ls1d1),(vulcan_ls0d2+vulcan_ls1d2),\
+ (vulcan_ls0d3+vulcan_ls1d3),vulcan_f01")
+
+(define_insn_reservation "vulcan_asimd_load3_elts" 7
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "neon_load3_one_lane,neon_load3_one_lane_q,\
+ neon_load3_all_lanes,neon_load3_all_lanes_q"))
+ "vulcan_ls_both,vulcan_l01delay,vulcan_f01")
+
+(define_insn_reservation "vulcan_asimd_load4_mult" 8
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "neon_load4_4reg,neon_load4_4reg_q"))
+ "vulcan_ls_both*4,(vulcan_ls0d1+vulcan_ls1d1),(vulcan_ls0d2+vulcan_ls1d2),\
+ (vulcan_ls0d3+vulcan_ls1d3),vulcan_f01")
+
+(define_insn_reservation "vulcan_asimd_load4_elts" 6
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "neon_load4_one_lane,neon_load4_one_lane_q,\
+ neon_load4_all_lanes,neon_load4_all_lanes_q"))
+ "vulcan_ls_both*2,(vulcan_ls0d1+vulcan_ls1d1),(vulcan_ls0d2+vulcan_ls1d2),\
+ (vulcan_ls0d3+vulcan_ls1d3),vulcan_f01")
+
+;; ASIMD store instructions.
+
+; Same note applies as for ASIMD load instructions.
+
+(define_insn_reservation "vulcan_asimd_store1_1_mult" 1
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "neon_store1_1reg,neon_store1_1reg_q"))
+ "vulcan_ls01")
+
+(define_insn_reservation "vulcan_asimd_store1_2_mult" 1
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "neon_store1_2reg,neon_store1_2reg_q"))
+ "vulcan_ls_both")
+
+(define_insn_reservation "vulcan_asimd_store1_3_mult" 1
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "neon_store1_3reg,neon_store1_3reg_q"))
+ "(vulcan_ls_both,vulcan_ls01)|(vulcan_ls01,vulcan_ls_both)")
+
+(define_insn_reservation "vulcan_asimd_store1_4_mult" 1
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "neon_store1_4reg,neon_store1_4reg_q"))
+ "vulcan_ls_both*2")
+
+(define_insn_reservation "vulcan_asimd_store1_onelane" 1
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "neon_store1_one_lane,neon_store1_one_lane_q"))
+ "vulcan_ls01,vulcan_f01")
+
+(define_insn_reservation "vulcan_asimd_store2_mult" 1
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "neon_store2_2reg,neon_store2_2reg_q"))
+ "vulcan_ls_both,vulcan_f01")
+
+(define_insn_reservation "vulcan_asimd_store2_onelane" 1
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "neon_store2_one_lane,neon_store2_one_lane_q"))
+ "vulcan_ls01,vulcan_f01")
+
+(define_insn_reservation "vulcan_asimd_store3_mult" 1
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "neon_store3_3reg,neon_store3_3reg_q"))
+ "vulcan_ls_both*3,vulcan_f01")
+
+(define_insn_reservation "vulcan_asimd_store3_onelane" 1
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "neon_store3_one_lane,neon_store3_one_lane_q"))
+ "vulcan_ls_both,vulcan_f01")
+
+(define_insn_reservation "vulcan_asimd_store4_mult" 1
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "neon_store4_4reg,neon_store4_4reg_q"))
+ "vulcan_ls_both*4,vulcan_f01")
+
+(define_insn_reservation "vulcan_asimd_store4_onelane" 1
+ (and (eq_attr "tune" "vulcan")
+ (eq_attr "type" "neon_store4_one_lane,neon_store4_one_lane_q"))
+ "vulcan_ls_both,vulcan_f01")
--
2.1.0
