On Mon, Jul 4, 2016 at 3:22 PM, Matthew Wahab
<matthew.wa...@foss.arm.com> wrote:
> On 17/05/16 15:52, Matthew Wahab wrote:
>> Support for using the half-precision floating point operations added by
>> the
>> ARMv8.2-A FP16 extension is based on the macros and intrinsics added to
>> the
>> ACLE for the extension.
>>
>> This patch adds executable tests for the ACLE Adv.SIMD (NEON) intrinsics
>> to
>> the advsimd-intrinsics testsuite.
>
> The tests added in the previous version of the patch, which only tested
> the f16 variants of intrinsics, are dropped. Instead, this patch extends
> the existing intrinsics tests to support the new f16 variants. Where the
> intrinsic is new, a new test for the intrinsic is added with f16 as the
> only variant. (This is consistent with existing practice, e.g vcvt.c.)
> The new tests are based on similar existing tests, e.g. maxnm_1.c is
> derived from max.c and the vcvt{a,m,p}_1.c tests, via vcvtX.inc, are
> based on vcvt.c.
>
> Since they are only available when the FP16 arithmetic instructions are
> enabled, advsimd-intrinsics.exp is updated to set -march=armv8.2+fp when
> the hardware supports it and the tests for the f16 intrinscs are guarded
> with __ARM_FEATURE_FP16_VECTOR_ARITHMETIC. Where a test has only f16
> variants, the test file itself is also guarded with
> dg-require-effective-target arm_v8_2a_fp16_neon_hw so that it reports
> UNSUPPORTED rather than PASS if FP16 isn't supported.
>
> Tested the series for arm-none-linux-gnueabihf with native bootstrap and
> make check and for arm-none-eabi and armeb-none-eabi with make check on
> an ARMv8.2-A emulator. Also tested the advsimd-intrinscs tests
> cross-compiled
> for aarch64-none-elf on an ARMv8.2-A emulator.
>
> Ok for trunk?OK. Thanks, Ramana > Matthew > > testsuite/ > 2016-07-04 Matthew Wahab <matthew.wa...@arm.com> > > * gcc.target/advsimd-intrinsics/advsimd-intrinsics.exp: Enable > -march=armv8.2-a+fp16 when supported by the hardware. > * gcc.target/aarch64/advsimd-intrinsics/binary_op_float.inc: New. > * gcc.target/aarch64/advsimd-intrinsics/binary_op_no64.inc: > Add F16 tests, enabled if macro HAS_FLOAT16_VARIANT is defined. Add > semi-colons to a macro invocations. > * gcc.target/aarch64/advsimd-intrinsics/cmp_fp_op.inc: Add F16 > tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is > defined. > * gcc.target/aarch64/advsimd-intrinsics/cmp_op.inc: Likewise. > * gcc.target/aarch64/advsimd-intrinsics/cmp_zero_op.inc: New. > * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vabd.c: Add F16 > tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is > defined. > * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vabs.c: Likewise. > * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vadd.c: Likewise. > * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vcage.c: > Likewise. > * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vcagt.c: > Likewise. > * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vcale.c: > Likewise. > * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vcalt.c: > Likewise. > * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vceq.c: Likewise. > * gcc.target/aarch64/advsimd-intrinsics/vceqz_1.c: New. > * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vcge.c: Add F16 > tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is > defined. > * gcc.target/aarch64/advsimd-intrinsics/vcgez_1.c: New. > * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vcgt.c: Add F16 > tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is > defined. > * gcc.target/aarch64/advsimd-intrinsics/vcgtz_1.c: New. > * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vcle.c: Add F16 > tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is > defined. > * gcc.target/aarch64/advsimd-intrinsics/vclez_1.c: New. > * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vclt.c: Add F16 > tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is > defined. > * gcc.target/aarch64/advsimd-intrinsics/vcltz_1.c: New. > * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vcvt.c: Add F16 > tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is > defined. Also fix some white-space. > * gcc.target/aarch64/advsimd-intrinsics/vcvtX.inc: New. > * gcc.target/aarch64/advsimd-intrinsics/vcvta_1.c: New. > * gcc.target/aarch64/advsimd-intrinsics/vcvtm_1.c: New. > * gcc.target/aarch64/advsimd-intrinsics/vcvtp_1.c: New. > * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vfma.c: Add F16 > tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is > defined. Also fix some long lines and white-space. > * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vfms.c: Add F16 > tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is > defined. Also fix some long lines and white-space. > * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vmax.c: Add F16 > tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is > defined. > * gcc.target/aarch64/advsimd-intrinsics/vmaxnm_1.c: New. > * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vmin.c: Add F16 > tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is > defined. > * gcc.target/aarch64/advsimd-intrinsics/vminnm_1.c: New. > * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vmul.c: Add F16 > tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is > defined. > * gcc.target/aarch64/advsimd-intrinsics/vmul_lane.c: Likewise. > * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vmul_n.c: > Likewise. > * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vneg.c: > Likewise. > * gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc: Likewise. > * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vpadd.c: > Likewise. > * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vpmax.c: > Likewise. > * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vpmin.c: > Likewise. > * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vrecpe.c: > Likewise. > * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vrecps.c: > Likewise. > * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vrnd.c: > Likewise. > * gcc.target/aarch64/advsimd-intrinsics/vrndX.inc: Likewise. > * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vrnda.c: > Likewise. > * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vrndm.c: > Likewise. > * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vrndn.c: > Likewise. > * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vrndp.c: > Likewise. > * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vrndx.c: > Likewise. > * gcc.target/aarch64/advsimd-intrinsics/vrsqrte.c: Likewise. > * gcc.target/aarch64/advsimd-intrinsics/vrsqrts.c: Likewise. > * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vsub.c: > Likewise. >
