On 9 August 2011 11:30, David Gilbert <david.gilb...@linaro.org> wrote: > Other than Ramana's comment about my comment on 4/4, has anyone else got any > other input? Otherwise I'd like to fix that comment and then get it in.
We now have comments from Ramana on patches 3/4 and 4/4 - anyone for anything on the main pair ? Dave > On 26 July 2011 09:59, Dr. David Alan Gilbert <david.gilb...@linaro.org> > wrote: >> Hi, >> This is V2 of a series of 4 patches relating to ARM atomic operations; >> they incorporate most of the feedback from V1 - thanks Ramana, Richard and >> Joseph for comments. >> >> 1) Provide 64 bit atomic operations using the new ldrexd/strexd in ARMv6k >> and above. >> 2) Provide fallbacks so that when compiled for earlier CPUs a Linux kernel >> asssist is called (as per 32bit and smaller ops) >> 3) Fix pr48126 which is a misplaced barrier in the atomic generation >> 4) Correct the definition of TARGET_HAVE_DMB_MCR so that it doesn't >> produce the mcr instruction in Thumb1 (and enable on ARMv6 not just 6k >> as per the docs). >> >> Relative to v1: >> Split the DMB_MCR patch out >> Provide complete changelogs >> Don't emit IT instruction except in Thumb2 mode >> Move iterators to iterators.md (didn't move the table since it was specific >> to sync.md) >> Remove sync_atleastsi >> Use sync_predtab in as many places as possible >> Avoid headers in libgcc >> Made various libgcc routines I added static >> used __write instead of write >> Comment the barrier move to explain it more >> >> Note that the kernel interface has remained the same for the helper, and as >> such I've not changed the way the helper calling in patch 2 is structured. >> >> This code was tested with a full bootstrap on ARM; make check results >> are the same as without the patches except for extra passes due to the new >> tests. >> >> This work is part of Linaro blueprint: >> https://blueprints.launchpad.net/linaro-toolchain-misc/+spec/64-bit-sync-primitives >> >> Dave >> >> >
