Hi Uros, > -----Original Message----- > From: Uros Bizjak [mailto:ubiz...@gmail.com] > Sent: Monday, August 22, 2016 12:36 AM > To: gcc-patches@gcc.gnu.org > Cc: Kumar, Venkataramanan <venkataramanan.ku...@amd.com>; NightStrike > StrikeNight <nightstr...@gmail.com> > Subject: [PATCH, i386]: Fine tune prefetchw emission (PR 77270) > > Hello! > > Attached patch fine-tunes the condition when prefetchw write prefetch insns > are emitted. prefetchw is preferred for non-SSE2 K7 athlons (this is covered > by > i386-prefetch.exp tests), on the other hand, SSE prefetches are preferred for > K8 > targets, as measured and reported in PR 77270. > > For newer targets, PRFCHW cpuid bit is respected, and -march=native correctly > emits prefetchw, when PRFCHW cpuid bit is set. (on a related note, > PTA_PRFCHW should probably be set for amdfam10+ targets, Venkataramanan > is looking into this issue).
Yes AMD family10 targets supports both 3DNowPrefetch (PTA_PRFCHW) and 3DNOW!. We should set PTA_PRFCHW for these targets. Patch was already posted few years back https://gcc.gnu.org/ml/gcc-patches/2012-09/msg00670.html Now we are not giving priority for prefetches via 3DNOW! ISA , we have to add PTA_PRFCHW for AMD fam10 targets. I have pushed the changes. https://gcc.gnu.org/viewcvs/gcc?view=revision&revision=239682 > > 2016-08-21 Uros Bizjak <ubiz...@gmail.com> > > PR target/77270 > * config/i386/i386.md (prefetch): When TARGET_PRFCHW or > TARGET_PREFETCHWT1 are disabled, emit 3dNOW! write prefetches for > non-SSE2 athlons only, otherwise prefer SSE prefetches. > > Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. > > Committed to mainline SVN. > > Uros. Regards, Venkat.
