On 11/30/2016 01:38 AM, Richard Biener wrote:
On Tue, Nov 29, 2016 at 5:07 PM, Jeff Law <l...@redhat.com> wrote:
On 11/29/2016 03:23 AM, Richard Biener wrote:

On Mon, Nov 28, 2016 at 10:23 PM, Jeff Law <l...@redhat.com> wrote:



I was digging into  issues around the patches for 78120 when I stumbled
upon
undesirable bb copying in bb-reorder.c on the m68k.

The core issue is that the m68k does not define a length attribute and
therefore generic code assumes that the length of all insns is 0 bytes.


What other targets behave like this?

ft32, nvptx, mmix, mn10300, m68k, c6x, rl78, vax, ia64, m32c

Ok.

cris has a hack to define a length, even though no attempt is made to make
it accurate.  The hack specifically calls out that it's to make bb-reorder
happy.


That in turn makes bb-reorder think it is infinitely cheap to copy basic
blocks.  In the two codebases I looked at (GCC's runtime libraries and
newlib) this leads to a 10% and 15% undesirable increase in code size.

I've taken a slight variant of this patch and bootstrapped/regression
tested
it on x86_64-linux-gnu to verify sanity as well as built the m68k target
libraries noted above.

OK for the trunk?


I wonder if it isn't better to default to a length of 1 instead of zero
when
there is no length attribute.  There are more users of the length
attribute
in bb-reorder.c (and elsewhere as well I suppose).

I pondered that as well, but felt it was riskier given we've had a default
length of 0 for ports that don't define lengths since the early 90s.  It's
certainly easy enough to change that default if you'd prefer.  I don't have
a strong preference either way.

Thinking about this again maybe targets w/o insn-length should simply
always use the 'simple' algorithm instead of the STV one?  At least that
might be what your change effectively does in some way?
From reading the comments I don't think STC will collapse down into the simple algorithm if block copying is disabled. But Segher would know for sure.

WRT the choice of simple vs STC, I doubt it matters much for the processors in question.

JEff

Reply via email to