On Fri, Dec 2, 2016 at 5:30 PM, Jakub Jelinek <ja...@redhat.com> wrote: > On Fri, Dec 02, 2016 at 05:12:20PM +0100, Uros Bizjak wrote: >> >> This patch: >> >> 1) adds one_cmpldi2 pattern for stv purposes (which splits into two >> >> one_cmplsi2 after reload) >> >> 2) teaches the 32-bit stv pass to handle NOT (as xor all-ones) >> >> 3) renames the old *andndi3_doubleword to *andndi3_doubleword_bmi, as it >> >> is for -mbmi only, and adds another *andndi3_doubleword pattern that is >> >> meant to live just from combine till the stv pass, or worse case till >> >> following split1 pass when it is split back into not followed by and; >> >> this change makes it possible to use pandn in stv pass, even without >> >> -mbmi >> > >> > Please use attached (lightly tested) patch to implement point 3) >> > above. The patch splits insn after reload, as is the case with all STV >> > patterns. >> >> Now attached for real. > > Ok, I've checked in following patch (compared to your notes just added > xfail to the pr70322-2.c test scan-assembler), feel free to test your patch > and remove the xfail again. > > 2016-12-02 Jakub Jelinek <ja...@redhat.com> > > PR target/70322 > * config/i386/i386.c (dimode_scalar_to_vector_candidate_p): Handle > NOT. > (dimode_scalar_chain::compute_convert_gain): Likewise. > (dimode_scalar_chain::convert_insn): Likewise. > * config/i386/i386.md (*one_cmpldi2_doubleword): New > define_insn_and_split. > (one_cmpl<mode>2): Use SWIM1248x iterator instead of SWIM. > > * gcc.target/i386/pr70322-1.c: New test. > * gcc.target/i386/pr70322-2.c: New test. > * gcc.target/i386/pr70322-3.c: New test.
Attached to this message, please find the patch that finally implements PANDN generation for non-BMI targets. 2016-12-02 Uros Bizjak <ubiz...@gmail.com> PR target/70322 * config/i386/i386.md (*andndi3_doubleword): Add non-BMI alternative and corresponding post-reload splitter. testsuite/ChangeLog: 2016-12-02 Uros Bizjak <ubiz...@gmail.com> PR target/70322 * gcc.target/i386/pr70322-2.c (dg-final): Remove xfail. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Committed to mainline SVN. Uros.
Index: config/i386/i386.md =================================================================== --- config/i386/i386.md (revision 243196) +++ config/i386/i386.md (working copy) @@ -8534,15 +8534,24 @@ operands[2] = gen_lowpart (QImode, operands[2]); }) -(define_insn_and_split "*andndi3_doubleword" - [(set (match_operand:DI 0 "register_operand" "=r") +(define_insn "*andndi3_doubleword" + [(set (match_operand:DI 0 "register_operand" "=r,&r") (and:DI - (not:DI (match_operand:DI 1 "register_operand" "r")) - (match_operand:DI 2 "nonimmediate_operand" "rm"))) + (not:DI (match_operand:DI 1 "register_operand" "r,0")) + (match_operand:DI 2 "nonimmediate_operand" "rm,rm"))) (clobber (reg:CC FLAGS_REG))] - "TARGET_BMI && !TARGET_64BIT && TARGET_STV && TARGET_SSE2" + "!TARGET_64BIT && TARGET_STV && TARGET_SSE2" "#" - "&& reload_completed" + [(set_attr "isa" "bmi,*")]) + +(define_split + [(set (match_operand:DI 0 "register_operand") + (and:DI + (not:DI (match_operand:DI 1 "register_operand")) + (match_operand:DI 2 "nonimmediate_operand"))) + (clobber (reg:CC FLAGS_REG))] + "!TARGET_64BIT && TARGET_BMI && TARGET_STV && TARGET_SSE2 + && reload_completed" [(parallel [(set (match_dup 0) (and:SI (not:SI (match_dup 1)) (match_dup 2))) (clobber (reg:CC FLAGS_REG))]) @@ -8551,6 +8560,24 @@ (clobber (reg:CC FLAGS_REG))])] "split_double_mode (DImode, &operands[0], 3, &operands[0], &operands[3]);") +(define_split + [(set (match_operand:DI 0 "register_operand") + (and:DI + (not:DI (match_dup 0)) + (match_operand:DI 1 "nonimmediate_operand"))) + (clobber (reg:CC FLAGS_REG))] + "!TARGET_64BIT && !TARGET_BMI && TARGET_STV && TARGET_SSE2 + && reload_completed" + [(set (match_dup 0) (not:SI (match_dup 0))) + (parallel [(set (match_dup 0) + (and:SI (match_dup 0) (match_dup 1))) + (clobber (reg:CC FLAGS_REG))]) + (set (match_dup 2) (not:SI (match_dup 2))) + (parallel [(set (match_dup 2) + (and:SI (match_dup 2) (match_dup 3))) + (clobber (reg:CC FLAGS_REG))])] + "split_double_mode (DImode, &operands[0], 2, &operands[0], &operands[2]);") + (define_insn "*andn<mode>_1" [(set (match_operand:SWI48 0 "register_operand" "=r,r") (and:SWI48 Index: testsuite/gcc.target/i386/pr70322-2.c =================================================================== --- testsuite/gcc.target/i386/pr70322-2.c (revision 243196) +++ testsuite/gcc.target/i386/pr70322-2.c (working copy) @@ -1,7 +1,7 @@ /* PR target/70322 */ /* { dg-do compile { target ia32 } } */ /* { dg-options "-O2 -msse2 -mstv -mno-bmi" } */ -/* { dg-final { scan-assembler "pandn" { xfail *-*-* } } } */ +/* { dg-final { scan-assembler "pandn" } } */ extern long long z;