On 01/17/2017 05:41 AM, Moore, Catherine wrote: > > >> -----Original Message----- >> From: Matthew Fortune [mailto:matthew.fort...@imgtec.com] >> Sent: Tuesday, January 17, 2017 4:35 AM >> ... >> Thanks for the comments. >> >> Having thought further I agree we can safely ignore DSP indexed load >> and micromips LWXS on >> the basis that DSP code will not run on a MIPS64 processor anyway (at >> least none that I >> know of) so the issue cannot occur and similarly for microMIPS, there >> are no 64-bit cores. >> >> Restricting to just LWXC1/SWXC1/LDXC1/SDXC1 is therefore fine but >> we should reflect >> that in option names then. >> >> --with-lxc1-sxc1 --without-lxc1-sxc1 >> -mlxc1-sxc1 >> >> These names reflect the internal macro that controls availability of >> these instructions. >> >> Macro name: __mips_no_lxc1_sxc1 >> Defined when !ISA_HAS_LXC1_SXC1 so would be present even when >> targeting a core that >> doesn't have the instructions anyway. >> >> Any refinements to this Catherine? >> > No. This plan looks good. > Hi Everyone,
I updated the patch accordingly. OK to commit? Thanks, Doug
>From 5aa6e7b837a281651ac1c6c58291c96d6ff25c53 Mon Sep 17 00:00:00 2001 From: Doug Gilmore <doug.gilm...@imgtec.com> Date: Wed, 11 Jan 2017 16:49:27 -0800 Subject: [PATCH] [MIPS] PR target/78176 add -mlxc1-sxc1. PR target/78176 * config.gcc (supported_defaults): Add lxc1-sxc1. (with_lxc1_sxc1): Add validation. (all_defaults): Add lxc1-sxc1. * config/mips/mips.opt (mlxc1-sxc1): New option. * gcc/config/mips/mips.h (OPTION_DEFAULT_SPECS): Add a default for mlxc1-sxc1. (TARGET_CPU_CPP_BUILTINS) Add builtin_define for __mips_no_lxc1_sxc1. ISA_HAS_LXC1_SXC1 gate with mips_lxc1_sxc1. * gcc/doc/invoke.texi (-mlxc1-sxc1): Document the new option. * doc/install.texi (--with-lxc1-sxc1): Document the new option. --- gcc/config.gcc | 19 +++++++++++++++++-- gcc/config/mips/mips.h | 8 ++++++-- gcc/config/mips/mips.opt | 4 ++++ gcc/doc/install.texi | 8 ++++++++ gcc/doc/invoke.texi | 6 ++++++ 5 files changed, 41 insertions(+), 4 deletions(-) diff --git a/gcc/config.gcc b/gcc/config.gcc index 7c27546..913e5c2 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -3940,7 +3940,7 @@ case "${target}" in ;; mips*-*-*) - supported_defaults="abi arch arch_32 arch_64 float fpu nan fp_32 odd_spreg_32 tune tune_32 tune_64 divide llsc mips-plt synci" + supported_defaults="abi arch arch_32 arch_64 float fpu nan fp_32 odd_spreg_32 tune tune_32 tune_64 divide llsc mips-plt synci lxc1-sxc1" case ${with_float} in "" | soft | hard) @@ -4063,6 +4063,21 @@ case "${target}" in exit 1 ;; esac + + case ${with_lxc1_sxc1} in + yes) + with_lxc1_sxc1=lxc1-sxc1 + ;; + no) + with_lxc1_sxc1=no-lxc1-sxc1 + ;; + "") + ;; + *) + echo "Unknown lxc1-sxc1 type used in --with-lxc1-sxc1" 1>&2 + exit 1 + ;; + esac ;; nds32*-*-*) @@ -4496,7 +4511,7 @@ case ${target} in esac t= -all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 schedule float mode fpu nan fp_32 odd_spreg_32 divide llsc mips-plt synci tls" +all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 schedule float mode fpu nan fp_32 odd_spreg_32 divide llsc mips-plt synci tls lxc1-sxc1" for option in $all_defaults do eval "val=\$with_"`echo $option | sed s/-/_/g` diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index f91b43d..6d9a7aa 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -637,6 +637,8 @@ struct mips_cpu_info { \ if (TARGET_CACHE_BUILTIN) \ builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \ + if (!ISA_HAS_LXC1_SXC1) \ + builtin_define ("__mips_no_lxc1_sxc1"); \ } \ while (0) @@ -866,7 +868,8 @@ struct mips_cpu_info { {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \ {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \ {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \ - {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" } + {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }, \ + {"lxc1-sxc1", "%{!mlxc1-sxc1:%{!mno-lxc1-sxc1:-m%(VALUE)}}" } \ /* A spec that infers the: -mnan=2008 setting from a -mips argument, @@ -1030,7 +1033,8 @@ struct mips_cpu_info { /* ISA has floating-point indexed load and store instructions (LWXC1, LDXC1, SWXC1 and SDXC1). */ -#define ISA_HAS_LXC1_SXC1 ISA_HAS_FP4 +#define ISA_HAS_LXC1_SXC1 (ISA_HAS_FP4 \ + && mips_lxc1_sxc1) /* ISA has paired-single instructions. */ #define ISA_HAS_PAIRED_SINGLE ((ISA_MIPS64 \ diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index 2559649..347f552 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -388,6 +388,10 @@ mlra Target Report Var(mips_lra_flag) Init(1) Save Use LRA instead of reload. +mlxc1-sxc1 +Target Report Var(mips_lxc1_sxc1) Init(1) +Use lxc1/sxc1 instructions where applicable. + mtune= Target RejectNegative Joined Var(mips_tune_option) ToLower Enum(mips_arch_opt_value) -mtune=PROCESSOR Optimize the output for PROCESSOR. diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi index 4958773..8757cf7b 100644 --- a/gcc/doc/install.texi +++ b/gcc/doc/install.texi @@ -1371,6 +1371,14 @@ On MIPS targets, make @option{-msynci} the default when no On MIPS targets, make @option{-mno-synci} the default when no @option{-msynci} option is passed. This is the default. +@item --with-lxc1-sxc1 +On MIPS targets, make @option{-mlxc1-sxc1} the default when no +@option{-mno-lxc1-sxc1} option is passed. This is the default. + +@item --without-lxc1-sxc1 +On MIPS targets, make @option{-mno-lxc1-sxc1} the default when no +@option{-mlxc1-sxc1} option is passed. + @item --with-mips-plt On MIPS targets, make use of copy relocations and PLTs. These features are extensions to the traditional diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 2bd105a..9991f4d 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -19856,6 +19856,12 @@ it is unused. This optimization is off by default at all optimization levels. +@item -mlxc1-sxc1 +@itemx -mno-lxc1-sxc1 +@opindex mlxc1-sxc1 +When applicable, enable (disable) the generation of lxc1/sxc1 +instructions. Enabled by default. + @end table @node MMIX Options -- 1.9.1