[PATCH][MIPS]MSA AND.d optimization to generate BCLRI.d

[Prachi Godbole]

Hi,

Below is the patch to fix ICE: output_operand: invalid use of '%V'
when generating BCLRI.d instruction from AND.d pattern.

Proposed fix:
mips_gen_const_int_vector (machine_mode mode, int val): Change type for 
argument VAL from int to HOST_WIDE_INT to allow const vector of type doubleword.
It is used by BCLRI.d alternative in AND.d pattern for immediate const vector 
operand with only one bit clear.

OK?

Changelog:

2017-03-06  Prachi Godbole  <prachi.godb...@imgtec.com>

gcc/
        * config/mips/mips.c (mips_gen_const_int_vector): Change type of last
        argument.
        * config/mips/mips-protos.h (mips_gen_const_int_vector): Likewise.

gcc/testsuite/
        * gcc.target/mips/msa-bclri.c: New test.


Index: config/mips/mips.c
===================================================================
--- config/mips/mips.c  (revision 245205)
+++ config/mips/mips.c  (working copy)
@@ -21608,7 +21608,7 @@
 /* Return a const_int vector of VAL with mode MODE.  */
 
 rtx
-mips_gen_const_int_vector (machine_mode mode, int val)
+mips_gen_const_int_vector (machine_mode mode, HOST_WIDE_INT val)
 {
   int nunits = GET_MODE_NUNITS (mode);
   rtvec v = rtvec_alloc (nunits);
Index: config/mips/mips-protos.h
===================================================================
--- config/mips/mips-protos.h   (revision 245205)
+++ config/mips/mips-protos.h   (working copy)
@@ -294,7 +294,7 @@
 extern bool mips_const_vector_bitimm_set_p (rtx, machine_mode);
 extern bool mips_const_vector_bitimm_clr_p (rtx, machine_mode);
 extern rtx mips_msa_vec_parallel_const_half (machine_mode, bool);
-extern rtx mips_gen_const_int_vector (machine_mode, int);
+extern rtx mips_gen_const_int_vector (machine_mode, HOST_WIDE_INT);
 extern bool mips_secondary_memory_needed (enum reg_class, enum reg_class,
                                          machine_mode);
 extern bool mips_cannot_change_mode_class (machine_mode,
Index: testsuite/gcc.target/mips/msa-bclri.c
===================================================================
--- testsuite/gcc.target/mips/msa-bclri.c       (revision 0)
+++ testsuite/gcc.target/mips/msa-bclri.c       (revision 0)
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mno-mips16 -mfp64 -mhard-float -mmsa" } */
+
+typedef long long v2i64 __attribute__ ((vector_size(16)));
+
+/* Test MSA AND.d optimization: generate BCLRI.d instead, for immediate const
+   vector operand with only one bit clear.  */
+
+void
+and_d_msa (v2i64 *vx, v2i64 *vy)
+{
+  v2i64 and_vec = {0x7FFFFFFFFFFFFFFF, 0x7FFFFFFFFFFFFFFF};
+  *vy = (*vx) & and_vec;
+}
+/* { dg-final { scan-assembler "bclri.d" } }  */