On Sun, 25 Sep 2011, David Miller wrote:
> I'll add a note about this to gcc-4.7/changes.html along with
> the FMAF stuff I'm about to commit.
Thanks for doing that, David. I believe my automated tester has
naged you over a small markup issue in the patch which I am
addressing thusly (together with some more markup).
Gerald
Index: changes.html
===================================================================
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-4.7/changes.html,v
retrieving revision 1.32
diff -u -r1.32 changes.html
--- changes.html 25 Sep 2011 22:39:05 -0000 1.32
+++ changes.html 25 Sep 2011 22:47:14 -0000
@@ -322,15 +322,16 @@
operations.</li>
<li>The compiler now properly tracks the <code>%gsr</code> register,
and how it behaves as an input for various VIS instructions.</li>
- <li>Akin to 'fzero', the compiler can now generate 'fone' instructions
- in order to set all of the bits of a floating-point register to
one.
+ <li>Akin to <code>fzero</code>, the compiler can now generate
+ <code>fone</code> instructions in order to set all of the bits
+ of a floating-point register to one.</li>
<li>The documentation for the VIS intrinsics in the GCC manual has
been brought up to date and many inaccuracies were fixed.</li>
</ul>
</li>
- <li>Support for UltraSPARC Fused Multiply-Add Floating-point
+ <li>Support for UltraSPARC Fused Multiply-Add floating-point
extensions has been added. These instructions are enabled by
- default on UltraSPARC T3 (Niagara 3) and later cpus.</li>
+ default on UltraSPARC T3 (Niagara 3) and later CPUs.</li>
</ul>
<h3 id="picochip">picochip</h3>
>
