On 12/04/17 14:08, Wilco Dijkstra wrote:
> All cores which add a cpu_addrcost_table use a non-zero value for
> HI and TI mode shifts (a non-zero value for general indexing also
> applies to all shifts). Given this, it makes no sense to use a
> different setting in generic_addrcost_table. So change it so that all
> supported cores, including -mcpu=generic, now generate the same:
>
That's not quite true: exynosm1_addrcost_table has 0 for HI but 2 for
TI; though use of TI here is a bit misleading as it essentially means
"any scaling that isn't 2, 4 or 8".
That being said, this change does seem to be closer to the more general
trend; furthermore, single scaled-offset mems are still merged into one
instruction.
OK.
R.
> int f(short *p, short *q, long x) { return p[x] + q[x]; }
>
> lsl x2, x2, 1
> ldrsh w3, [x0, x2]
> ldrsh w0, [x1, x2]
> add w0, w3, w0
> ret
>
> Bootstrapped for AArch64. Any comments? OK for stage 1?
>
> ChangeLog:
> 2017-04-12 Wilco Dijkstra <wdijk...@arm.com>
>
> * gcc/config/aarch64/aarch64.c (generic_addrcost_table):
> Change HI/TI mode setting.
>
> ---
> diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
> index
> 419b756efcb40e48880cd4529efc4f9f59938325..728ce7029f1e2b5161d9f317d10e564dd5a5f472
> 100644
> --- a/gcc/config/aarch64/aarch64.c
> +++ b/gcc/config/aarch64/aarch64.c
> @@ -193,10 +193,10 @@ static const struct aarch64_flag_desc
> aarch64_tuning_flags[] =
> static const struct cpu_addrcost_table generic_addrcost_table =
> {
> {
> - 0, /* hi */
> + 1, /* hi */
> 0, /* si */
> 0, /* di */
> - 0, /* ti */
> + 1, /* ti */
> },
> 0, /* pre_modify */
> 0, /* post_modify */
>
