On Wed, Apr 26, 2017 at 02:33:56PM -0400, Michael Meissner wrote:
> This patch is meant for GCC 8. While GCC 7 has branched, I plan to wait
> until it is actually released before applying these patches. But if you would
> prefer me to submit them sooner, I can do it.
>
> This patch, addresses the remaining issues on 3 PRs (79038, 79202, and 79203).
> Since these issues were inter-related, I am tackling them via a combined
> patch.
> PR 79038 (integer <-> IEEE 128 fp conversions) is pretty much answered with
> previous changes.
>
> This patch addresses PR 79202 (use vector instructions for sign extension of
> 32-bit integers on pre-ISA 3.0 systems (ISA 3.0 has an appropriate sign
> extension instruction). It also addresses PR 79203 (have fp conversion know
> that 32-bit integers can go in vector registers on ISA 2.07, and 8/16-bit
> integers can go in vector registers on ISA 3.0), and replaces UNSPECs with
> more
> normal moves, etc.
>
> On Spec 2006, it gives minor (1%) gains on the int benchmark astar, and also
> 1%
> gains on the floating point povray and sphinx3 benchmarks. There were no
> significant regressions in performance with these patches on the other
> benchmarks in Spec 2006.
>
> Once gcc7 is released, can I check this into the gcc8 trunk? I would like to
> back port these changes to gcc 7 for GCC 7.2 as well. These patches depend on
> the small integer support, which is not in GCC 6, so they would not be
> appropriate for GCC 6.
This is okay for trunk now. Thanks! Also okay for the 7 branch,
after the usual burn-in.
Segher
> [gcc]
> 2017-04-26 Michael Meissner <meiss...@linux.vnet.ibm.com>
>
> PR target/79038
> PR target/79202
> PR target/79203
> * config/rs6000/rs6000.md (u code attribute): Add FIX and
> UNSIGNED_FIX.
> (extendsi<mode>2): Add support for doing sign extension via
> VUPKHSW and XXPERMDI if the value is in Altivec registers and we
> don't have ISA 3.0 instructions.
> (extendsi<mode>2 splitter): Likewise.
> (fix_trunc<mode>si2): If we are at ISA 2.07 (VSX small integer),
> generate the normal insns since SImode can now go in vector
> registers. Disallow the special UNSPECs needed for previous
> machines to hide SImode being used. Add new insns
> fctiw{,w}_<mode>_smallint if SImode can go in vector registers.
> (fix_trunc<mode>si2_stfiwx): Likewise.
> (fix_trunc<mode>si2_internal): Likewise.
> (fixuns_trunc<mode>si2): Likewise.
> (fixuns_trunc<mode>si2_stfiwx): Likewise.
> (fctiw<u>z_<mode>_smallint): Likewise.
> (fctiw<u>z_<mode>_mem): New combiner pattern to prevent conversion
> of floating point to 32-bit integer from doing a direct move to
> the GPR registers to do a store.
> (fctiwz_<mode>): Break long line.
>
> [gcc/testsuite]
> 2017-04-26 Michael Meissner <meiss...@linux.vnet.ibm.com>
>
> PR target/79038
> PR target/79202
> PR target/79203
> * gcc.target/powerpc/ppc-round3.c: New test.
> * gcc.target/powerpc/ppc-round2.c: Update expected code.
