Richard Earnshaw (lists) wrote: > On 05/05/17 13:42, Wilco Dijkstra wrote: >> Richard Earnshaw (lists) wrote: >>> On 04/05/17 18:38, Wilco Dijkstra wrote: >>> > Richard Earnshaw wrote: >>> > >>>>> - 5, /* Max cond insns. */ >>>>> + 2, /* Max cond insns. */ >>>> >>>>> This parameter is also used for A32 code. Is that really the right >>>>> number there as well? >>>> >>>> Yes, this parameter has always been the same for ARM and Thumb-2. >>> >>> I know that. I'm questioning whether that number (2) is right when on >>> ARM. It seems very low to me, especially when branches are unpredictable. >> >> Why does it seem low? Benchmarking showed 2 was the best value for modern >> cores. The same branch predictor is used, so the same settings should be >> used >> for ARM and Thumb-2. > > Thumb2 code has to execute an additional instruction to start an IT > sequence. It might therefore seem reasonable for the ARM sequence to be > one instruction longer.
The IT instruction has no inputs/outputs and thus behaves like a NOP - unlike conditional instructions which have real latencies and additional dependencies due to being conditional. So the overhead of IT itself is small. Wilco
