If we cannot load a constant into a register in one insn, and that
constant is a valid mask (for rotate instructions), we currently
prefer to load -1 and then mask it. This patch makes us not do that if
instead we could use two add or or instructions, since those are
sometimes faster on certain CPUs (and never are slower).
Tested on powerpc64-linux {-m32,-m64}, committing to trunk.
Segher
2017-05-19 Segher Boessenkool <seg...@kernel.crashing.org>
* config/rs6000/rs6000.md (splitter to load of -1 and mask): Don't
use this splitter if two add or or instructions would also work for
the constant we want to generate.
---
gcc/config/rs6000/rs6000.md | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 0a806b3..b7eedf2 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -8704,6 +8704,7 @@ (define_split
(match_operand:DI 1 "const_int_operand"))]
"TARGET_POWERPC64
&& num_insns_constant (operands[1], DImode) > 1
+ && !IN_RANGE (INTVAL (operands[1]), -0x80000000, 0xffffffff)
&& rs6000_is_valid_and_mask (operands[1], DImode)"
[(set (match_dup 0)
(const_int -1))
--
1.9.3
