Hi Carl,
On Wed, Jul 12, 2017 at 04:08:20PM -0700, Carl Love wrote:
> * config/rs6000/vsx.md(vsx_xvcvhpsp): Add define_insn.
Space before (.
> +;; Generate xvcvhpsp instruction
> +(define_insn "vsx_xvcvhpsp"
> + [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa")
> + (unspec:V4SF [(match_operand: V8HI 1 "vsx_register_operand" "f")]
> + UNSPEC_VSX_CVHPSP))]
> + "VECTOR_UNIT_VSX_P (V4SFmode)"
> + "xvcvhpsp %x0,%x1"
> + [(set_attr "type" "fp")])
Is there anything here that restricts this to ISA 3.0 and later?
Directly, I mean; nothing will generate this otherwise, but that is
kind of fragile.
Why "f" as contraint? Won't this work on any VSX register?
Is type "fp" a good type for this (for p9 scheduling)?
> +;; Generate vector extract four float 32 values from left four elements
> +;; of eight element vector of float 16 values.
> +(define_expand "vextract_fp_from_shorth"
> + [(set (match_operand:V4SF 0 "register_operand" "=v")
> + (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "v")]
> + UNSPEC_VSX_VEXTRACT_FP_FROM_SHORTH))]
> + "TARGET_P9_VECTOR"
> +{
> + int vals[16] = {0, 1, 0 ,0, 2, 3, 0, 0, 4, 5, 0, 0, 6, 7, 0, 8};
s/ ,/, /
Is that 8 correct, shouldn't it be 0?
Is "v" best (won't "wa" work)?
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/builtins-3-p9-runnable.c
> @@ -0,0 +1,36 @@
> +/* { dg-do run { target { powerpc64*-*-* && { lp64 && p9vector_hw } } } } */
> +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } {
> "-mcpu=power9" } } */
> +/* { dg-require-effective-target powerpc_p9vector_ok } */
Do you need this although you have p9vector_hw already?
Segher
