On Wed, Jul 26, 2017 at 06:41:23AM -0500, Segher Boessenkool wrote: > > That is to follow aarch64 iterator naming convention, where they have > > Ugh, for some reason I thought this was in rs6000/ as well. I have > fresh coffee now. Sorry.
Apparently I broke power bootstrap with this, because two new spots were introduced after I wrote the patch and my cross-compiler which didn't have HAVE_AS_POWER9 defined didn't reveal that. Fixed thusly, committed as obvious to trunk: 2017-08-01 Jakub Jelinek <ja...@redhat.com> PR target/80846 * config/rs6000/vsx.md (vextract_fp_from_shorth, vextract_fp_from_shortl): Add element mode after mode in gen_vec_init* calls. --- gcc/config/rs6000/vsx.md.jj 2017-07-28 09:10:49.000000000 +0200 +++ gcc/config/rs6000/vsx.md 2017-08-01 18:04:50.000000000 +0200 @@ -4523,7 +4523,7 @@ (define_expand "vextract_fp_from_shorth" inputs in half words 1,3,5,7 (IBM numbering). Use xxperm to move src half words 0,1,2,3 for the conversion instruction. */ v = gen_rtvec_v (16, rvals); - emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v))); + emit_insn (gen_vec_initv16qiqi (mask, gen_rtx_PARALLEL (V16QImode, v))); emit_insn (gen_altivec_vperm_v8hiv16qi (tmp, operands[1], operands[1], mask)); emit_insn (gen_vsx_xvcvhpsp (operands[0], tmp)); @@ -4552,7 +4552,7 @@ (define_expand "vextract_fp_from_shortl" inputs in half words 1,3,5,7 (IBM numbering). Use xxperm to move src half words 4,5,6,7 for the conversion instruction. */ v = gen_rtvec_v (16, rvals); - emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v))); + emit_insn (gen_vec_initv16qiqi (mask, gen_rtx_PARALLEL (V16QImode, v))); emit_insn (gen_altivec_vperm_v8hiv16qi (tmp, operands[1], operands[1], mask)); emit_insn (gen_vsx_xvcvhpsp (operands[0], tmp)); Jakub