These testcase assume -mcpu=generic or -march=armv8.1-a so use those
options as needed.
Note gcc.target/aarch64/target_attr_3.c needs both as it depends on
scheduler to get the pattern needed for fix-cortex-a53-835769 to work.
Committed after testing on aarch64-linux-gnu with
--target_board=unix/\{,-mcpu=thunderx,-mcpu=thunderx2t99,-march=armv8-a,-march=armv8.1-a,-march=armv8.2-a\}
and saw no failures.
Thanks,
Andrew Pinski
ChangeLog:
* gcc.target/aarch64/target_attr_10.c: Add -mcpu=generic.
* gcc.target/aarch64/target_attr_13.c: LIkewise.
* gcc.target/aarch64/target_attr_15.c: LIkewise.
* gcc.target/aarch64/target_attr_4.c: Likewise.
* gcc.target/aarch64/target_attr_1.c: Add -march=armv8-a.
* gcc.target/aarch64/target_attr_2.c: Likewise.
* gcc.target/aarch64/target_attr_7.c: Likewise.
* gcc.target/aarch64/target_attr_crypto_ice_1.c: Likewise.
* gcc.target/aarch64/target_attr_crypto_ice_2.c: Likewise.
* gcc.target/aarch64/target_attr_3.c: Add -mcpu=generic -march=armv8-a.
Index: testsuite/gcc.target/aarch64/target_attr_10.c
===================================================================
--- testsuite/gcc.target/aarch64/target_attr_10.c (revision 250901)
+++ testsuite/gcc.target/aarch64/target_attr_10.c (working copy)
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -march=armv8-a+simd" } */
+/* { dg-options "-O2 -march=armv8-a+simd -mcpu=generic" } */
/* Using a SIMD intrinsic from a function tagged with nosimd should fail
due to inlining rules. */
Index: testsuite/gcc.target/aarch64/target_attr_13.c
===================================================================
--- testsuite/gcc.target/aarch64/target_attr_13.c (revision 250901)
+++ testsuite/gcc.target/aarch64/target_attr_13.c (working copy)
@@ -1,5 +1,5 @@
/* { dg-do assemble } */
-/* { dg-options "-O2 -march=armv8-a+crc+crypto" } */
+/* { dg-options "-O2 -march=armv8-a+crc+crypto -mcpu=generic" } */
#include "arm_acle.h"
Index: testsuite/gcc.target/aarch64/target_attr_15.c
===================================================================
--- testsuite/gcc.target/aarch64/target_attr_15.c (revision 250901)
+++ testsuite/gcc.target/aarch64/target_attr_15.c (working copy)
@@ -1,5 +1,5 @@
/* { dg-do assemble } */
-/* { dg-options "-march=armv8-a+crypto -save-temps" } */
+/* { dg-options "-march=armv8-a+crypto -mcpu=generic -save-temps" } */
/* Check that "+nothing" clears the ISA flags. */
Index: testsuite/gcc.target/aarch64/target_attr_1.c
===================================================================
--- testsuite/gcc.target/aarch64/target_attr_1.c (revision 250901)
+++ testsuite/gcc.target/aarch64/target_attr_1.c (working copy)
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -mcpu=thunderx -dA" } */
+/* { dg-options "-O2 -mcpu=thunderx -march=armv8-a -dA" } */
/* Test that cpu attribute overrides the command-line -mcpu. */
Index: testsuite/gcc.target/aarch64/target_attr_2.c
===================================================================
--- testsuite/gcc.target/aarch64/target_attr_2.c (revision 250901)
+++ testsuite/gcc.target/aarch64/target_attr_2.c (working copy)
@@ -1,5 +1,5 @@
/* { dg-do assemble } */
-/* { dg-options "-O2 -mcpu=cortex-a57 -ftree-vectorize -fdump-tree-vect-all" }
*/
+/* { dg-options "-O2 -mcpu=cortex-a57 -march=armv8-a -ftree-vectorize
-fdump-tree-vect-all" } */
/* The various ways to turn off simd availability should
turn off vectorization. */
Index: testsuite/gcc.target/aarch64/target_attr_3.c
===================================================================
--- testsuite/gcc.target/aarch64/target_attr_3.c (revision 250901)
+++ testsuite/gcc.target/aarch64/target_attr_3.c (working copy)
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -mno-fix-cortex-a53-835769 -save-temps" } */
+/* { dg-options "-O2 -mno-fix-cortex-a53-835769 -march=armv8-a -mcpu=generic
-save-temps" } */
/* Check that the attribute overrides the command line option
and the fix is applied once. */
Index: testsuite/gcc.target/aarch64/target_attr_4.c
===================================================================
--- testsuite/gcc.target/aarch64/target_attr_4.c (revision 250901)
+++ testsuite/gcc.target/aarch64/target_attr_4.c (working copy)
@@ -1,5 +1,5 @@
/* { dg-do assemble } */
-/* { dg-options "-O2 -march=armv8-a+nocrc -save-temps" } */
+/* { dg-options "-O2 -march=armv8-a+nocrc -mcpu=generic -save-temps" } */
#include "arm_acle.h"
Index: testsuite/gcc.target/aarch64/target_attr_7.c
===================================================================
--- testsuite/gcc.target/aarch64/target_attr_7.c (revision 250901)
+++ testsuite/gcc.target/aarch64/target_attr_7.c (working copy)
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -mcpu=thunderx -dA" } */
+/* { dg-options "-O2 -mcpu=thunderx -march=armv8-a -dA" } */
/* Make sure that #pragma overrides command line option and
target attribute overrides the pragma. */
Index: testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c
===================================================================
--- testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c (revision
250901)
+++ testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c (working copy)
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -mcpu=thunderx+nofp" } */
+/* { dg-options "-O2 -mcpu=thunderx+nofp -march=armv8-a" } */
#include "arm_neon.h"
Index: testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c
===================================================================
--- testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c (revision
250901)
+++ testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c (working copy)
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -mcpu=thunderx+nofp" } */
+/* { dg-options "-O2 -mcpu=thunderx+nofp -march=armv8-a" } */
/* Make sure that we don't ICE when dealing with vector parameters
in a simd-tagged function within a non-simd translation unit. */
