Hi All, This patch adds support for the +dotprod extension to ARM. Dot Product requires Adv.SIMD to work and so enables this option by default when enabled.
It is available from ARMv8.2-a and onwards and is enabled by default on Cortex-A55 and Cortex-A75. Regtested and bootstrapped on arm-none-eabi and no issues. Ok for trunk? gcc/ 2017-09-01 Tamar Christina <tamar.christ...@arm.com> * config/arm/arm.h (TARGET_DOTPROD): New. * config/arm/arm.c (arm_arch_dotprod): New. (arm_option_reconfigure_globals): Add arm_arch_dotprod. * config/arm/arm-c.c (__ARM_FEATURE_DOTPROD): New. * config/arm/arm-cpus.in (cortex-a55, cortex-75): Enabled +dotprod. (armv8.2-a, cortex-a75.cortex-a55): Likewise. * config/arm/arm-isa.h (isa_bit_dotprod, ISA_DOTPROD): New. * config/arm/t-multilib (v8_2_a_simd_variants): Add dotprod. * doc/invoke.texi (armv8.2-a): Document dotprod --
diff --git a/gcc/config/arm/arm-c.c b/gcc/config/arm/arm-c.c index 55472434c3a6e90c5693bbaabd3265f7d968787f..295f03bf8ee02be7c89ed2967d283be206e9f25a 100644 --- a/gcc/config/arm/arm-c.c +++ b/gcc/config/arm/arm-c.c @@ -73,6 +73,7 @@ arm_cpu_builtins (struct cpp_reader* pfile) def_or_undef_macro (pfile, "__ARM_FEATURE_QRDMX", TARGET_NEON_RDMA); def_or_undef_macro (pfile, "__ARM_FEATURE_CRC32", TARGET_CRC32); + def_or_undef_macro (pfile, "__ARM_FEATURE_DOTPROD", TARGET_DOTPROD); def_or_undef_macro (pfile, "__ARM_32BIT_STATE", TARGET_32BIT); cpp_undef (pfile, "__ARM_FEATURE_CMSE"); diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index d009a9e18acb093aefe0f9d8d6de49489fc2325c..7707eec5edf36b0cb4339bc52bc45a92b6ea007f 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -357,6 +357,7 @@ begin arch armv8.2-a option crypto add FP_ARMv8 CRYPTO option nocrypto remove ALL_CRYPTO option nofp remove ALL_FP + option dotprod add FP_ARMv8 DOTPROD end arch armv8.2-a begin arch armv8-m.base @@ -1269,9 +1270,10 @@ begin cpu cortex-a55 cname cortexa55 tune for cortex-a53 tune flags LDSCHED - architecture armv8.2-a+fp16 + architecture armv8.2-a+fp16+dotprod fpu neon-fp-armv8 option crypto add FP_ARMv8 CRYPTO + option dotprod add FP_ARMv8 DOTPROD option nofp remove ALL_FP costs cortex_a53 end cpu cortex-a55 @@ -1280,9 +1282,10 @@ begin cpu cortex-a75 cname cortexa75 tune for cortex-a57 tune flags LDSCHED - architecture armv8.2-a+fp16 + architecture armv8.2-a+fp16+dotprod fpu neon-fp-armv8 option crypto add FP_ARMv8 CRYPTO + option dotprod add FP_ARMv8 DOTPROD costs cortex_a73 end cpu cortex-a75 @@ -1292,9 +1295,10 @@ begin cpu cortex-a75.cortex-a55 cname cortexa75cortexa55 tune for cortex-a53 tune flags LDSCHED - architecture armv8.2-a+fp16 + architecture armv8.2-a+fp16+dotprod fpu neon-fp-armv8 option crypto add FP_ARMv8 CRYPTO + option dotprod add FP_ARMv8 DOTPROD costs cortex_a73 end cpu cortex-a75.cortex-a55 diff --git a/gcc/config/arm/arm-isa.h b/gcc/config/arm/arm-isa.h index dbd29eaa52f2007498c2aff6263b8b6c3a70e2c2..60a50edf08dd7d3ac9ad46967250f4dcc6b8768b 100644 --- a/gcc/config/arm/arm-isa.h +++ b/gcc/config/arm/arm-isa.h @@ -66,6 +66,7 @@ enum isa_feature isa_bit_fp_d32, /* 32 Double precision registers. */ isa_bit_crypto, /* Crypto extension to ARMv8. */ isa_bit_fp16, /* FP16 data processing (half-precision float). */ + isa_bit_dotprod, /* Dot Product instructions. */ /* ISA Quirks (errata?). Don't forget to add this to the list of all quirks below. */ @@ -159,6 +160,7 @@ enum isa_feature #define ISA_FP_ARMv8 ISA_FPv5, ISA_FP_D32 #define ISA_NEON ISA_FP_D32, isa_bit_neon #define ISA_CRYPTO ISA_NEON, isa_bit_crypto +#define ISA_DOTPROD ISA_NEON, isa_bit_dotprod /* List of all quirk bits to strip out when comparing CPU features with architectures. */ diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 4f53583cf0219de4329bc64a47a5a42c550ff354..44a95bf7eb2eab8e3cf07ac9cc7aad3d9997b27f 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -210,6 +210,11 @@ extern tree arm_fp16_type_node; /* FPU supports ARMv8.1 Adv.SIMD extensions. */ #define TARGET_NEON_RDMA (TARGET_NEON && arm_arch8_1) +/* Supports for Dot Product AdvSIMD extensions. */ +#define TARGET_DOTPROD (TARGET_NEON \ + && bitmap_bit_p (arm_active_target.isa, \ + isa_bit_dotprod)) + /* FPU supports the floating point FP16 instructions for ARMv8.2 and later. */ #define TARGET_VFP_FP16INST \ (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP5 && arm_fp16_inst) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 71379dd5afc4c0dd62fdafd08777793d2ad47ae7..486591137f95cfb2e51adb7082f346edf84449de 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -952,6 +952,9 @@ int arm_condexec_masklen = 0; /* Nonzero if chip supports the ARMv8 CRC instructions. */ int arm_arch_crc = 0; +/* Nonzero if chip supports the AdvSIMD Dot Product instructions. */ +int arm_arch_dotprod = 0; + /* Nonzero if chip supports the ARMv8-M security extensions. */ int arm_arch_cmse = 0; @@ -3594,6 +3597,8 @@ arm_option_reconfigure_globals (void) arm_arch_cmse = bitmap_bit_p (arm_active_target.isa, isa_bit_cmse); arm_fp16_inst = bitmap_bit_p (arm_active_target.isa, isa_bit_fp16); arm_arch_lpae = bitmap_bit_p (arm_active_target.isa, isa_bit_lpae); + arm_arch_dotprod = bitmap_bit_p (arm_active_target.isa, isa_bit_dotprod); + if (arm_fp16_inst) { if (arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE) diff --git a/gcc/config/arm/t-multilib b/gcc/config/arm/t-multilib index ec4b76dbc8fc56093c2b27c95e0947558496fe5a..47f3673160a766c5b1b8972f7670355f2c357b56 100644 --- a/gcc/config/arm/t-multilib +++ b/gcc/config/arm/t-multilib @@ -68,7 +68,7 @@ v7ve_vfpv4_simd_variants := +simd v8_a_nosimd_variants := +crc v8_a_simd_variants := $(call all_feat_combs, simd crypto) v8_1_a_simd_variants := $(call all_feat_combs, simd crypto) -v8_2_a_simd_variants := $(call all_feat_combs, simd fp16 crypto) +v8_2_a_simd_variants := $(call all_feat_combs, simd fp16 crypto dotprod) ifneq (,$(HAS_APROFILE)) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 64363e54a00c56a3de545735620189f7ec0cde04..4cb5836a9da22681d192c3750fc8e5a50024ac10 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -15492,6 +15492,10 @@ The ARMv8.1 Advanced SIMD and floating-point instructions. The cryptographic instructions. This also enables the Advanced SIMD and floating-point instructions. +@item +dotprod +Enable the Dot Product extension. This also enables Advanced SIMD instructions +and allows auto vectorization of dot products to the Dot Product instructions. + @item +nocrypto Disable the cryptographic extension.