This patch passes the number of units to aarch64_simd_vect_par_cnst_half, which avoids a to_constant () once GET_MODE_NUNITS is variable.
2017-10-27 Richard Sandiford <richard.sandif...@linaro.org> Alan Hayward <alan.hayw...@arm.com> David Sherwood <david.sherw...@arm.com> gcc/ * config/aarch64/aarch64-protos.h (aarch64_simd_vect_par_cnst_half): Take the number of units too. * config/aarch64/aarch64.c (aarch64_simd_vect_par_cnst_half): Likewise. (aarch64_simd_check_vect_par_cnst_half): Update call accordingly, but check for a vector mode before rather than after the call. * config/aarch64/aarch64-simd.md (aarch64_split_simd_mov<mode>) (move_hi_quad_<mode>, vec_unpack<su>_hi_<mode>) (vec_unpack<su>_lo_<mode, vec_widen_<su>mult_lo_<mode>) (vec_widen_<su>mult_hi_<mode>, vec_unpacks_lo_<mode>) (vec_unpacks_hi_<mode>, aarch64_saddl2<mode>, aarch64_uaddl2<mode>) (aarch64_ssubl2<mode>, aarch64_usubl2<mode>, widen_ssum<mode>3) (widen_usum<mode>3, aarch64_saddw2<mode>, aarch64_uaddw2<mode>) (aarch64_ssubw2<mode>, aarch64_usubw2<mode>, aarch64_sqdmlal2<mode>) (aarch64_sqdmlsl2<mode>, aarch64_sqdmlal2_lane<mode>) (aarch64_sqdmlal2_laneq<mode>, aarch64_sqdmlsl2_lane<mode>) (aarch64_sqdmlsl2_laneq<mode>, aarch64_sqdmlal2_n<mode>) (aarch64_sqdmlsl2_n<mode>, aarch64_sqdmull2<mode>) (aarch64_sqdmull2_lane<mode>, aarch64_sqdmull2_laneq<mode>) (aarch64_sqdmull2_n<mode>): Update accordingly. Index: gcc/config/aarch64/aarch64-protos.h =================================================================== --- gcc/config/aarch64/aarch64-protos.h 2017-10-27 14:12:04.192082112 +0100 +++ gcc/config/aarch64/aarch64-protos.h 2017-10-27 14:12:07.203885483 +0100 @@ -403,7 +403,7 @@ const char *aarch64_output_move_struct ( rtx aarch64_return_addr (int, rtx); rtx aarch64_simd_gen_const_vector_dup (machine_mode, HOST_WIDE_INT); bool aarch64_simd_mem_operand_p (rtx); -rtx aarch64_simd_vect_par_cnst_half (machine_mode, bool); +rtx aarch64_simd_vect_par_cnst_half (machine_mode, int, bool); rtx aarch64_tls_get_addr (void); tree aarch64_fold_builtin (tree, int, tree *, bool); unsigned aarch64_dbx_register_number (unsigned); Index: gcc/config/aarch64/aarch64.c =================================================================== --- gcc/config/aarch64/aarch64.c 2017-10-27 14:12:04.193939530 +0100 +++ gcc/config/aarch64/aarch64.c 2017-10-27 14:12:07.205742901 +0100 @@ -12007,12 +12007,12 @@ aarch64_simd_scalar_immediate_valid_for_ Low Mask: { 2, 3 } { 0, 1 } High Mask: { 0, 1 } { 2, 3 } -*/ + + MODE Is the mode of the vector and NUNITS is the number of units in it. */ rtx -aarch64_simd_vect_par_cnst_half (machine_mode mode, bool high) +aarch64_simd_vect_par_cnst_half (machine_mode mode, int nunits, bool high) { - int nunits = GET_MODE_NUNITS (mode); rtvec v = rtvec_alloc (nunits / 2); int high_base = nunits / 2; int low_base = 0; @@ -12041,14 +12041,15 @@ aarch64_simd_vect_par_cnst_half (machine aarch64_simd_check_vect_par_cnst_half (rtx op, machine_mode mode, bool high) { - rtx ideal = aarch64_simd_vect_par_cnst_half (mode, high); + if (!VECTOR_MODE_P (mode)) + return false; + + rtx ideal = aarch64_simd_vect_par_cnst_half (mode, GET_MODE_NUNITS (mode), + high); HOST_WIDE_INT count_op = XVECLEN (op, 0); HOST_WIDE_INT count_ideal = XVECLEN (ideal, 0); int i = 0; - if (!VECTOR_MODE_P (mode)) - return false; - if (count_op != count_ideal) return false; Index: gcc/config/aarch64/aarch64-simd.md =================================================================== --- gcc/config/aarch64/aarch64-simd.md 2017-10-27 14:12:04.193010821 +0100 +++ gcc/config/aarch64/aarch64-simd.md 2017-10-27 14:12:07.203885483 +0100 @@ -252,8 +252,8 @@ (define_expand "aarch64_split_simd_mov<m { rtx dst_low_part = gen_lowpart (<VHALF>mode, dst); rtx dst_high_part = gen_highpart (<VHALF>mode, dst); - rtx lo = aarch64_simd_vect_par_cnst_half (<MODE>mode, false); - rtx hi = aarch64_simd_vect_par_cnst_half (<MODE>mode, true); + rtx lo = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, false); + rtx hi = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true); emit_insn (gen_aarch64_simd_mov_from_<mode>low (dst_low_part, src, lo)); @@ -1436,7 +1436,7 @@ (define_expand "move_hi_quad_<mode>" (match_operand:<VHALF> 1 "register_operand" "")] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, false); + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, false); if (BYTES_BIG_ENDIAN) emit_insn (gen_aarch64_simd_move_hi_quad_be_<mode> (operands[0], operands[1], p)); @@ -1520,7 +1520,7 @@ (define_expand "vec_unpack<su>_hi_<mode> (ANY_EXTEND:<VWIDE> (match_operand:VQW 1 "register_operand"))] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true); + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true); emit_insn (gen_aarch64_simd_vec_unpack<su>_hi_<mode> (operands[0], operands[1], p)); DONE; @@ -1532,7 +1532,7 @@ (define_expand "vec_unpack<su>_lo_<mode> (ANY_EXTEND:<VWIDE> (match_operand:VQW 1 "register_operand" ""))] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, false); + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, false); emit_insn (gen_aarch64_simd_vec_unpack<su>_lo_<mode> (operands[0], operands[1], p)); DONE; @@ -1652,7 +1652,7 @@ (define_expand "vec_widen_<su>mult_lo_<m (ANY_EXTEND:<VWIDE> (match_operand:VQW 2 "register_operand" ""))] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, false); + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, false); emit_insn (gen_aarch64_simd_vec_<su>mult_lo_<mode> (operands[0], operands[1], operands[2], p)); @@ -1679,7 +1679,7 @@ (define_expand "vec_widen_<su>mult_hi_<m (ANY_EXTEND:<VWIDE> (match_operand:VQW 2 "register_operand" ""))] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true); + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true); emit_insn (gen_aarch64_simd_vec_<su>mult_hi_<mode> (operands[0], operands[1], operands[2], p)); @@ -2083,7 +2083,7 @@ (define_expand "vec_unpacks_lo_<mode>" (match_operand:VQ_HSF 1 "register_operand" "")] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, false); + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, false); emit_insn (gen_aarch64_simd_vec_unpacks_lo_<mode> (operands[0], operands[1], p)); DONE; @@ -2106,7 +2106,7 @@ (define_expand "vec_unpacks_hi_<mode>" (match_operand:VQ_HSF 1 "register_operand" "")] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true); + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true); emit_insn (gen_aarch64_simd_vec_unpacks_lo_<mode> (operands[0], operands[1], p)); DONE; @@ -3027,7 +3027,7 @@ (define_expand "aarch64_saddl2<mode>" (match_operand:VQW 2 "register_operand" "w")] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true); + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true); emit_insn (gen_aarch64_saddl<mode>_hi_internal (operands[0], operands[1], operands[2], p)); DONE; @@ -3039,7 +3039,7 @@ (define_expand "aarch64_uaddl2<mode>" (match_operand:VQW 2 "register_operand" "w")] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true); + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true); emit_insn (gen_aarch64_uaddl<mode>_hi_internal (operands[0], operands[1], operands[2], p)); DONE; @@ -3051,7 +3051,7 @@ (define_expand "aarch64_ssubl2<mode>" (match_operand:VQW 2 "register_operand" "w")] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true); + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true); emit_insn (gen_aarch64_ssubl<mode>_hi_internal (operands[0], operands[1], operands[2], p)); DONE; @@ -3063,7 +3063,7 @@ (define_expand "aarch64_usubl2<mode>" (match_operand:VQW 2 "register_operand" "w")] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true); + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true); emit_insn (gen_aarch64_usubl<mode>_hi_internal (operands[0], operands[1], operands[2], p)); DONE; @@ -3089,7 +3089,7 @@ (define_expand "widen_ssum<mode>3" (match_operand:<VDBLW> 2 "register_operand" "")))] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, false); + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, false); rtx temp = gen_reg_rtx (GET_MODE (operands[0])); emit_insn (gen_aarch64_saddw<mode>_internal (temp, operands[2], @@ -3117,7 +3117,7 @@ (define_expand "widen_usum<mode>3" (match_operand:<VDBLW> 2 "register_operand" "")))] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, false); + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, false); rtx temp = gen_reg_rtx (GET_MODE (operands[0])); emit_insn (gen_aarch64_uaddw<mode>_internal (temp, operands[2], @@ -3178,7 +3178,7 @@ (define_expand "aarch64_saddw2<mode>" (match_operand:VQW 2 "register_operand" "w")] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true); + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true); emit_insn (gen_aarch64_saddw2<mode>_internal (operands[0], operands[1], operands[2], p)); DONE; @@ -3190,7 +3190,7 @@ (define_expand "aarch64_uaddw2<mode>" (match_operand:VQW 2 "register_operand" "w")] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true); + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true); emit_insn (gen_aarch64_uaddw2<mode>_internal (operands[0], operands[1], operands[2], p)); DONE; @@ -3203,7 +3203,7 @@ (define_expand "aarch64_ssubw2<mode>" (match_operand:VQW 2 "register_operand" "w")] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true); + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true); emit_insn (gen_aarch64_ssubw2<mode>_internal (operands[0], operands[1], operands[2], p)); DONE; @@ -3215,7 +3215,7 @@ (define_expand "aarch64_usubw2<mode>" (match_operand:VQW 2 "register_operand" "w")] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true); + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true); emit_insn (gen_aarch64_usubw2<mode>_internal (operands[0], operands[1], operands[2], p)); DONE; @@ -3735,7 +3735,7 @@ (define_expand "aarch64_sqdmlal2<mode>" (match_operand:VQ_HSI 3 "register_operand" "w")] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true); + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true); emit_insn (gen_aarch64_sqdmlal2<mode>_internal (operands[0], operands[1], operands[2], operands[3], p)); DONE; @@ -3748,7 +3748,7 @@ (define_expand "aarch64_sqdmlsl2<mode>" (match_operand:VQ_HSI 3 "register_operand" "w")] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true); + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true); emit_insn (gen_aarch64_sqdmlsl2<mode>_internal (operands[0], operands[1], operands[2], operands[3], p)); DONE; @@ -3816,7 +3816,7 @@ (define_expand "aarch64_sqdmlal2_lane<mo (match_operand:SI 4 "immediate_operand" "i")] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true); + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true); emit_insn (gen_aarch64_sqdmlal2_lane<mode>_internal (operands[0], operands[1], operands[2], operands[3], operands[4], p)); @@ -3831,7 +3831,7 @@ (define_expand "aarch64_sqdmlal2_laneq<m (match_operand:SI 4 "immediate_operand" "i")] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true); + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true); emit_insn (gen_aarch64_sqdmlal2_laneq<mode>_internal (operands[0], operands[1], operands[2], operands[3], operands[4], p)); @@ -3846,7 +3846,7 @@ (define_expand "aarch64_sqdmlsl2_lane<mo (match_operand:SI 4 "immediate_operand" "i")] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true); + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true); emit_insn (gen_aarch64_sqdmlsl2_lane<mode>_internal (operands[0], operands[1], operands[2], operands[3], operands[4], p)); @@ -3861,7 +3861,7 @@ (define_expand "aarch64_sqdmlsl2_laneq<m (match_operand:SI 4 "immediate_operand" "i")] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true); + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true); emit_insn (gen_aarch64_sqdmlsl2_laneq<mode>_internal (operands[0], operands[1], operands[2], operands[3], operands[4], p)); @@ -3894,7 +3894,7 @@ (define_expand "aarch64_sqdmlal2_n<mode> (match_operand:<VEL> 3 "register_operand" "w")] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true); + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true); emit_insn (gen_aarch64_sqdmlal2_n<mode>_internal (operands[0], operands[1], operands[2], operands[3], p)); @@ -3908,7 +3908,7 @@ (define_expand "aarch64_sqdmlsl2_n<mode> (match_operand:<VEL> 3 "register_operand" "w")] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true); + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true); emit_insn (gen_aarch64_sqdmlsl2_n<mode>_internal (operands[0], operands[1], operands[2], operands[3], p)); @@ -4062,7 +4062,7 @@ (define_expand "aarch64_sqdmull2<mode>" (match_operand:VQ_HSI 2 "register_operand" "w")] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true); + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true); emit_insn (gen_aarch64_sqdmull2<mode>_internal (operands[0], operands[1], operands[2], p)); DONE; @@ -4123,7 +4123,7 @@ (define_expand "aarch64_sqdmull2_lane<mo (match_operand:SI 3 "immediate_operand" "i")] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true); + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true); emit_insn (gen_aarch64_sqdmull2_lane<mode>_internal (operands[0], operands[1], operands[2], operands[3], p)); @@ -4137,7 +4137,7 @@ (define_expand "aarch64_sqdmull2_laneq<m (match_operand:SI 3 "immediate_operand" "i")] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true); + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true); emit_insn (gen_aarch64_sqdmull2_laneq<mode>_internal (operands[0], operands[1], operands[2], operands[3], p)); @@ -4170,7 +4170,7 @@ (define_expand "aarch64_sqdmull2_n<mode> (match_operand:<VEL> 2 "register_operand" "w")] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true); + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true); emit_insn (gen_aarch64_sqdmull2_n<mode>_internal (operands[0], operands[1], operands[2], p)); DONE;