The following patch creates a new insn type to annotate quad precision
multiply instructions, updates the appropriate insns to use the new type
and creates an entry in the Power9 machine description which describes
the correct latency/resources. Bootstrap/regtest on powerpc64le-linux
with no new regressions. Ok for trunk?
-Pat
2017-11-08 Pat Haugen <pthau...@us.ibm.com>
* rs6000/power9.md (power9-qpmul): New.
* rs6000/rs6000.md ("type" attr): Add qmul.
(mul<mode>3, fma<mode>4_hw, *fms<mode>4_hw, *nfma<mode>4_hw,
*nfms<mode>4_hw, mul<mode>3_odd, fma<mode>4_odd, *fms<mode>4_odd,
*nfma<mode>4_odd, *nfms<mode>4_odd): Change type to qmul.
Index: gcc/config/rs6000/power9.md
===================================================================
--- gcc/config/rs6000/power9.md (revision 254377)
+++ gcc/config/rs6000/power9.md (working copy)
@@ -436,6 +436,12 @@ (define_insn_reservation "power9-qpdiv"
(eq_attr "cpu" "power9"))
"DU_super_power9,dfu_power9")
+(define_insn_reservation "power9-qpmul" 24
+ (and (eq_attr "type" "qmul")
+ (eq_attr "size" "128")
+ (eq_attr "cpu" "power9"))
+ "DU_super_power9,dfu_power9*12")
+
(define_insn_reservation "power9-mffgpr" 2
(and (eq_attr "type" "mffgpr")
(eq_attr "cpu" "power9"))
Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md (revision 254377)
+++ gcc/config/rs6000/rs6000.md (working copy)
@@ -182,7 +182,7 @@ (define_attr "type"
cmp,
branch,jmpreg,mfjmpr,mtjmpr,trap,isync,sync,load_l,store_c,
cr_logical,delayed_cr,mfcr,mfcrf,mtcr,
- fpcompare,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,
+ fpcompare,fp,fpsimple,dmul,qmul,sdiv,ddiv,ssqrt,dsqrt,
vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,
vecfloat,vecfdiv,vecdouble,mffgpr,mftgpr,crypto,
veclogical,veccmpfx,vecexts,vecmove,
@@ -14230,7 +14230,7 @@ (define_insn "mul<mode>3"
(match_operand:IEEE128 2 "altivec_register_operand" "v")))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsmulqp %0,%1,%2"
- [(set_attr "type" "vecfloat")
+ [(set_attr "type" "qmul")
(set_attr "size" "128")])
(define_insn "div<mode>3"
@@ -14332,7 +14332,7 @@ (define_insn "fma<mode>4_hw"
(match_operand:IEEE128 3 "altivec_register_operand" "0")))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsmaddqp %0,%1,%2"
- [(set_attr "type" "vecfloat")
+ [(set_attr "type" "qmul")
(set_attr "size" "128")])
(define_insn "*fms<mode>4_hw"
@@ -14344,7 +14344,7 @@ (define_insn "*fms<mode>4_hw"
(match_operand:IEEE128 3 "altivec_register_operand" "0"))))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsmsubqp %0,%1,%2"
- [(set_attr "type" "vecfloat")
+ [(set_attr "type" "qmul")
(set_attr "size" "128")])
(define_insn "*nfma<mode>4_hw"
@@ -14356,7 +14356,7 @@ (define_insn "*nfma<mode>4_hw"
(match_operand:IEEE128 3 "altivec_register_operand" "0"))))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsnmaddqp %0,%1,%2"
- [(set_attr "type" "vecfloat")
+ [(set_attr "type" "qmul")
(set_attr "size" "128")])
(define_insn "*nfms<mode>4_hw"
@@ -14369,7 +14369,7 @@ (define_insn "*nfms<mode>4_hw"
(match_operand:IEEE128 3 "altivec_register_operand" "0")))))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsnmsubqp %0,%1,%2"
- [(set_attr "type" "vecfloat")
+ [(set_attr "type" "qmul")
(set_attr "size" "128")])
(define_insn "extend<SFDF:mode><IEEE128:mode>2_hw"
@@ -14644,7 +14644,7 @@ (define_insn "mul<mode>3_odd"
UNSPEC_MUL_ROUND_TO_ODD))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsmulqpo %0,%1,%2"
- [(set_attr "type" "vecfloat")
+ [(set_attr "type" "qmul")
(set_attr "size" "128")])
(define_insn "div<mode>3_odd"
@@ -14677,7 +14677,7 @@ (define_insn "fma<mode>4_odd"
UNSPEC_FMA_ROUND_TO_ODD))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsmaddqpo %0,%1,%2"
- [(set_attr "type" "vecfloat")
+ [(set_attr "type" "qmul")
(set_attr "size" "128")])
(define_insn "*fms<mode>4_odd"
@@ -14690,7 +14690,7 @@ (define_insn "*fms<mode>4_odd"
UNSPEC_FMA_ROUND_TO_ODD))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsmsubqpo %0,%1,%2"
- [(set_attr "type" "vecfloat")
+ [(set_attr "type" "qmul")
(set_attr "size" "128")])
(define_insn "*nfma<mode>4_odd"
@@ -14703,7 +14703,7 @@ (define_insn "*nfma<mode>4_odd"
UNSPEC_FMA_ROUND_TO_ODD)))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsnmaddqpo %0,%1,%2"
- [(set_attr "type" "vecfloat")
+ [(set_attr "type" "qmul")
(set_attr "size" "128")])
(define_insn "*nfms<mode>4_odd"
@@ -14717,7 +14717,7 @@ (define_insn "*nfms<mode>4_odd"
UNSPEC_FMA_ROUND_TO_ODD)))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsnmsubqpo %0,%1,%2"
- [(set_attr "type" "vecfloat")
+ [(set_attr "type" "qmul")
(set_attr "size" "128")])
(define_insn "trunc<mode>df2_odd"
